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Original question:

TDA4VM: DSI support in PSDKLA

TDA4VM: TDA4VM DSI support on Linux

John Weber
Intellectual 511 points
Part Number: TDA4VM
Other Parts Discussed in Thread: TDA4VL, AB15

Hi,

We want to use MIPI-DSI output from the TDA4VM instead of DisplayPort. The simple reason is that we want to allow for a display interface AND also have access to SERDES4 to use as SGMII or QSGMII to supply 4 ports of GbE from the CPSW9G.  If using DisplayPort, the TX lanes of SERDES4 would be consumed with the DP function.

From this post, dated over 1 year ago, it is explained that DSI is not supported in Linux, and there are no plans to in the future:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1005337/tda4vm-dsi-support-in-psdkla

However, from the following e2e post, it seems that TI intended to add support for DSI in SDK 8.4:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1113577/tda4vm-tda4vm-dsi-support-in-psdkla-with-sdk-version-ti-processor-sdk-linux-j7-evm-08_02_00_03?tisearch=e2e-sitesearch&keymatch=TDA4VM%252520MIPI%252520DSI%252520Linux#

But, the latest PSDK Linux Release Notes (8.4) it seems that DSI is not supported:

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-rt-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html

Having DSI support would allow for much more cost-effective LCD panels to be directly connected to TDA4VM. In addition, expansion to LVDS, HDMI, and FPDLinkIII is also very possible. Our use case involves using this as an HMI, not a camera preview screen, so it makes much more sense to use Linux rather than RTOS to drive it.

What is the plan for adding DSI support to Linux on J7?

Thanks!

  • 0
    TI__Guru**** 475245 points

    Hi ,

    I think it should have been supported already, Let me check internally with the team and get back to you on this. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 511 points

    Hi Brijesh,

    After checking 8.04, we are able to locate some references to MIPI-DSI in the DTS. This implies that support has indeed been added, even if the release notes indicate otherwise.

    Do you know if this is tested with a display?

    Thanks!

  • 0 in reply to John Weber
    TI__Guru**** 475245 points

    Hi ,

    Yes, this is validated, but on TDA4VL device, i think you could use same device nodes to check it even on TDA4VM. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 450 points

    Hi, Brijesh:

    Could you give us some clues about how to set up clocks, power domains and interrupts in dsi node for TDA4VM?

    dsi0: dsi@4800000 {
                    compatible = "ti,j721e-dsi";
                    reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
                    clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
                    clock-names = "dsi_p_clk", "dsi_sys_clk";
                    power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
                    interrupt-parent = <&gic500>;
                    interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
                    phys = <&dphy0>;
                    phy-names = "dphy";

                    dsi0_ports: ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
                            port@0 {
                                    reg = <0>;
                            };
                            port@1 {
                                    reg = <1>;
                            };
                    };
            };

    BR,

    Richard

  • 0 in reply to Brijesh Jadav
    Intellectual 450 points

    Hi, Brijesh:

    I am working on enabling LVDS panel via DS90UB941/DS90UB948 our custom TDA4VM board.

    TDA4VM (MIPI DSI 4 lanes)-> DS90SUB941 ->(FPDLINK)  DS90UB948 ->(LVDS) 1280x800 panel


    We have enabled it on NXP i.mx8MP platform successfully.
    On TDA4VM, I run into trouble that DSI panel can't 'pass mode_valid' in cdns-dsi-core.c and always fails in 'phy_validate'.

    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    kern  :debug : [drm:drm_sysfs_connector_add] adding "DSI-1" to sysfs
    kern  :debug : [drm:drm_sysfs_hotplug_event] generating hotplug event
    kern  :info  : [drm] Initialized tidss 1.0.0 20180215 for 4a00000.dss on minor 0
    kern  :debug : [drm:drm_client_modeset_probe]
    kern  :debug : [drm:drm_mode_object_get] OBJ ID: 39 (2)
    kern  :debug : [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:DSI-1]
    kern  :debug : [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:DSI-1] status updated from unknown to connected
                   --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_mode_valid, Line:249
                   --->cdns_dsi_check_conf - start
                   --->cdns_dsi_check_conf - cdns_dsi_mode2cfg
                   --->cdns_dsi_check_conf - phy_mipi_dphy_get_default_config
                   --->cdns_dsi_adjust_phy_config - cdns_dsi_adjust_phy_config
                   --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_adjust_phy_config, Line:129
                   --->cdns_dsi_adjust_phy_config, lane number: 4
                   --->cdns_dsi_adjust_phy_config - phy_validate
                   --->cdns_dsi_bridge_mode_valid - MODE_BAD
    kern  :debug : [drm:drm_mode_debug_printmodeline] Modeline "1280x800": 58 68900 1280 1320 1400 1440 800 803 813 823 0x48 0xa
    kern  :debug : [drm:drm_mode_prune_invalid] Not using 1280x800 mode: BAD
    kern  :debug : [drm:drm_client_modeset_probe] No connectors reported connected with modes
    kern  :debug : [drm:drm_client_modeset_probe] connector 39 enabled? yes
    kern  :debug : [drm:drm_client_modeset_probe] Not using firmware configuration
    kern  :debug : [drm:drm_client_modeset_probe] looking for cmdline mode on connector 39
    kern  :debug : [drm:drm_client_modeset_probe] looking for preferred mode on connector 39 0
    kern  :debug : [drm:drm_client_modeset_probe] found mode none
    kern  :debug : [drm:drm_client_modeset_probe] picking CRTCs for 8096x8096 config
    kern  :debug : [drm:drm_mode_object_put.part.3] OBJ ID: 39 (2)
    kern  :debug : tidss 4a00000.dss: [drm:__drm_fb_helper_initial_config_and_unlock] test CRTC 0 primary plane
    kern  :info  : tidss 4a00000.dss: [drm] Cannot find any crtc or sizes

    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    And there is no DSI clock output shown on oscilloscope.
    We can only see backlight to be enabled. It explains the configuration for SERDES panel takes effect.
    I have tried to mark   'phy_validate' check in cdns-dsi-core.c.
    But there is still no DSI clock output.

    We can measure the DSI clock on NXP i.mx8MP.

    The measure clock 213MHz corresponds to the bit clock.
    bit clock(bitclk) = htotal x vtotal x 60 x (bpp) / (lane number) 
                           = 1440 x 823 x 60 x 24 / 4 =  426,643,200 = 426 MHz
    Because the MIPI clock is DDR trigger. So the measured clock frequency is half of bit clock data rate.
    426 MHz / 2 =213 MHz

    To enable MIPI DSI support, i modify:
    1. I apply the DSI related patch from k3-j721e-main.dts.
    https://github.com/TechNexion-customization/linux-ti/commit/c9d231f24fc7c726919fb75453c91d1b28dc2f7b

    2. Add display timing setting in 'drivers/gpu/drm/panel/panel-simple.c'
    https://github.com/TechNexion-customization/linux-ti/commit/13f14b309407046c43f22af54e025119ec2bd9c2

    3. Add device tree overlay to enable panel
    https://github.com/TechNexion-customization/linux-ti/commit/558bbb76379a786b4fc728ae1bca1ebc67905b0d

    My question is how to make cdns-dsi-core pass 'phy_validate'? How does it mean when it fails in 'phy_validate'?

    Is there any example to demonstrate CDNS DSI of TDA4VM? (e.g. a MIPI panel works with panel-simpl and cdns-dsi drivers. )
    Then, although i don't have physical panel, i still can measure DSI clock output to prove DSI controller working.

    Thanks~!!!

    BR,

    Richard

  • 0 in reply to Richard Hu
    Intellectual 450 points

    I follow the change below to add crtc_clock, crtc_hdisplay in 'drm_display_mode' setting in 'panel-simple.c', crtc_htotal...then cdns-dsi-core can pass 'phy_validate'.

    https://github.com/beagleboard/linux/commit/77f3db77d12b545326d33a9d7e2807da16af4f2f

    Here is the change i made:

    https://github.com/TechNexion-customization/linux-ti/commit/ac541020a6b17cddfed7fa8ee97da24e9d07d359

    But i still can't measure DSI clock on scope.

    I get no bus_formats message from tidss and i will try to solve it.

    root@j7-evm:~# systemctl stop weston
    root@j7-evm:~# [   35.689557] tidss 4a00000.dss: tidss_encoder_atomic_check: No bus_formats in connected display
    [   35.701290] tidss 4a00000.dss: tidss_encoder_atomic_check: No bus_formats in connected display
    root@j7-evm:~# kmsprint
    Connector 0 (39) DSI-1 (connected)
    [   43.305264] tidss 4a00000.dss: tidss_encoder_atomic_check: No bus_formats in connected display
      Encoder 0 (38) NONE
    root@j7-evm:~# kmstest -c 0
    Connector 0/@39: DSI-1[   51.854265] tidss 4a00000.dss: tidss_encoder_atomic_check: No bus_formats in connected display
      Crtc 0/@37: 1280x800 68.900 1280/40/80/40/- 800/3/10/10/- 58[   51.864986] tidss 4a00000.dss: tidss_encoder_atomic_check: No bus_formats in connected display
    (58.14) 0xa 0x48
      Plane 0/@31: 0,0-1280x800
        Fb 59 1280x800-XR24
    Atomic test failed: -22

    I notice beaglebone AI 64 change to use VESA timing for RPI 7 inch panel.

    Is it required for CDNS DSI driver?

    Is any other possible reason to result in no DSI clock output?

    BR,

    Richard

  • 0 in reply to Richard Hu
    Intellectual 450 points

    After i specify bus format in custom panel in panel-simple.c, i can see there is DSI clock output:

    https://github.com/TechNexion-customization/linux-ti/commit/b0c027c8a48ab786e22a841545a6eddf272f085d

    But the display still show nothing. I will keep working on it.

  • 0 in reply to Richard Hu
    Intellectual 450 points

    I can get LVDS clock output from DES.

    But there is still nothing shown on display.

    Not sure what kind of problem causes no display.

    When i execute kmstest, then DSI clock stops.

    Is it correct? it should output test pattern if the display works.
    root@j7-evm:~# systemctl stop weston
    root@j7-evm:~# kmsprint
    Connector 0 (39) DSI-1 (connected)
      Encoder 0 (38) NONE
        Crtc 0 (37) 1280x800 68.900 1280/40/80/40 800/3/10/10 58 (58.14)
          Plane 0 (31) fb-id: 58 (crtcs: 0) 0,0 1280x800 -> 0,0 1280x800 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
            FB 58 1280x800
    root@j7-evm:~# kmstest -c 0
    [  288.495604] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.501335] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.506822] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.512310] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.517794] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.523280] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.528954] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.534481] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.539974] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    [  288.545453] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
    Connector 0/@39: DSI-1[  288.558305] tidss 4a00000.dss: vp2: Clock rate 600000000 differs over 5% from requested 68900000
      Crtc 0/@37: 1280x800 68.900 1280/40/80/40/- 800/3/10/10/- 58 (58.14) 0xa 0x48
      Plane 0/@31: 0,0-1280x800
        Fb 59 1280x800-XR24
    press enter to exit
    root@j7-evm:~# kms-steal-crtc /dev/dri/card0
    Using screen DSI-0, resolution 1280x800

    BR,

    Richard

  • 0 in reply to Richard Hu
    TI__Genius 14625 points

    Hi Richard:

    I'm checking this E2E with TI RnD.

    Before the conclusion made, I think this might be the root cause.  tidss 4a00000.dss: vp2: Clock rate 600000000 differs over 5% from requested 68900000

    Can you check the clock setting?

    THanks.

    BR Rio

  • 0 in reply to Rio Chan
    TI__Genius 14625 points

    Maybe to low down this value for a try ? ==> .crtc_clock = 68900, /* 68900, */

  • 0 in reply to Rio Chan
    Intellectual 450 points

    Thanks for the feedback.

    I have tried to increase pixel clock to 71000kHz and decrease to 67900kHz and set exact 68900kHz clock.
    It looks no difference. I still get black display.


    Update the latest status:

    On custom TDA4VM board, i can measure the DSI clock output and LVDS clock output on oscilloscope.

    (DSI clock output form TDA4VM is about 213 MHz as below )

    But i don't see there is DSI data output shown oscilloscope as below.

    I think it might be the root cause to make there is black display shown on the screen.

    We have enabled SERDES panel on NXP i.mx8mp.

    We can get clear DSI clock and DSI data output from i.mx8mp.

    (DSI clock output from i.mx8mp as below.)

    (DSI data output from imx8mp as below.)

    My question is:

    1. I am not sure what did i miss to enable TI DSS and DSI to make there is no DSI data output.

    Here is the change i made.

    https://github.com/TechNexion-customization/linux-ti/commits/tn-ti_5.10.120_08.04.00.005-next-dsi-vizionpanel

    2. We understand DSI is not support on TDA4VM in 08.04.00 BSP and enable custom panel is our duty.

    But could you give us an example or demonstration how to enable a DSI panel with panel-simple-dsi driver(panel-simple.c).

    Thus, even i don't have your panel on hand, i still can measure DSI clock and data output to ensure DSS and DSI work properly.

    BR,

    Richard

  • 0 in reply to Richard Hu
    TI__Genius 14625 points

    Hi Richard:

    Thanks for your fast reply.

    Our RND is finding the correct patch for this issue.

    We will come back to you asap.

    BR Rio

  • 0 in reply to Richard Hu
    TI__Guru**** 475245 points

    Hi Richard,

    DSI gets the input data from the DSS, so in order to get the data output from DSI, we need to send some data via DSS. Can you please use below command to send some data? 

    kmstest

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 450 points

    Fullscreen modetest_-M_tidss_on_custom_tda4vm_20221012.txt Download 
    modetest -M tidss
[   73.322170]
[   73.322170] --->panel_simple_get_non_edid_modes, start
[   73.329096]
[   73.329096] --->panel_simple_get_non_edid_modes, panel_simple_get_display_modes
[   73.338146]
[   73.338146] --->panel_simple_get_non_edid_modes, panel->desc->bpc = 8
[   73.346309]
[   73.346309] --->panel_simple_get_non_edid_modes, panel->desc->size.width = 161
[   73.355252]
[   73.355252] --->panel_simple_get_non_edid_modes, panel->desc->size.height = 243
[   73.364278]
[   73.364278] --->panel_simple_get_non_edid_modes, drm_display_info_set_bus_formats
[   73.373486]
[   73.373486] --->panel_simple_get_non_edid_modes, finish
[   73.380440]
[   73.380440] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_mode_valid, Line:251
[   73.392505]
[   73.392505] --->cdns_dsi_check_conf - start
[   73.398324]
[   73.398324] --->cdns_dsi_check_conf - cdns_dsi_mode2cfg
[   73.405185]
[   73.405185] --->cdns_dsi_check_conf - phy_mipi_dphy_get_default_config
[   73.413346]
[   73.413346] --->cdns_dsi_adjust_phy_config - cdns_dsi_adjust_phy_config
[   73.421595]
[   73.421595] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_adjust_phy_config, Line:129
[   73.433655]
[   73.433655] --->cdns_dsi_adjust_phy_config, lane number: 4
[   73.440862]
[   73.440862] --->cdns_dsi_adjust_phy_config - phy_validate
[   73.447904]
[   73.447904] --->cdns_dsi_adjust_phy_config - mode_to_dpi_hfp
[   73.455226]
[   73.455226] --->cdns_dsi_adjust_phy_config - done
Encoders:
id      crtc    type    possible crtcs  possible clones
38      37      none    0x00000001      0x00000001

Connectors:
id      encoder status          name            size (mm)       modes   encoders
39      38      connected       DSI-1           161x243         1       38
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  #0 1280x800 56.53 1280 1328 1360 1440 800 803 809 823 67000 flags: ; type: preferred, driver
  props:
        1 EDID:
                flags: immutable blob
                blobs:

                value:
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
        5 link-status:
                flags: enum
                enums: Good=0 Bad=1
                value: 0
        6 non-desktop:
                flags: immutable range
                values: 0 1
                value: 0
        4 TILE:
                flags: immutable blob
                blobs:

                value:
        20 CRTC_ID:
                flags: object
                value: 37

CRTCs:
id      fb      pos     size
37      60      (0,0)   (1280x800)
  #0 1280x800 56.53 1280 1328 1360 1440 800 803 809 823 67000 flags: ; type: preferred, driver
  props:
        22 ACTIVE:
                flags: range
                values: 0 1
                value: 1
        23 MODE_ID:
                flags: blob
                blobs:

                value:
                        b8050100000530055005a00500002003
                        23032903370300003900000000000000
                        48000000313238307838303000000000
                        00000000000000000000000000000000
                        00000000
        19 OUT_FENCE_PTR:
                flags: range
                values: 0 18446744073709551615
                value: 0
        24 VRR_ENABLED:
                flags: range
                values: 0 1
                value: 0
        27 CTM:
                flags: blob
                blobs:

                value:
        28 GAMMA_LUT:
                flags: blob
                blobs:

                value:
        29 GAMMA_LUT_SIZE:
                flags: immutable range
                values: 0 4294967295
                value: 256

Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
31      37      60      0,0             0,0     0               0x00000001
  formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        17 FB_ID:
                flags: object
                value: 60
        18 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        20 CRTC_ID:
                flags: object
                value: 37
        13 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        14 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        15 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 1280
        16 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 800
        9 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        10 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        11 SRC_W:
                flags: range
                values: 0 4294967295
                value: 83886080
        12 SRC_H:
                flags: range
                values: 0 4294967295
                value: 52428800
        32 zpos:
                flags: range
                values: 0 3
                value: 0
        33 COLOR_ENCODING:
                flags: enum
                enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                value: 0
        34 COLOR_RANGE:
                flags: enum
                enums: YCbCr limited range=0 YCbCr full range=1
                value: 0
        35 alpha:
                flags: range
                values: 0 65535
                value: 65535
        36 pixel blend mode:
                flags: enum
                enums: Pre-multiplied=0 Coverage=1
                value: 0
40      0       0       0,0             0,0     0               0x00000001
  formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 0
        17 FB_ID:
                flags: object
                value: 0
        18 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        20 CRTC_ID:
                flags: object
                value: 0
        13 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        14 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        15 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 0
        16 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 0
        9 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        10 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        11 SRC_W:
                flags: range
                values: 0 4294967295
                value: 0
        12 SRC_H:
                flags: range
                values: 0 4294967295
                value: 0
        41 zpos:
                flags: range
                values: 0 3
                value: 0
        42 COLOR_ENCODING:
                flags: enum
                enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                value: 0
        43 COLOR_RANGE:
                flags: enum
                enums: YCbCr limited range=0 YCbCr full range=1
                value: 0
        44 alpha:
                flags: range
                values: 0 65535
                value: 65535
        45 pixel blend mode:
                flags: enum
                enums: Pre-multiplied=0 Coverage=1
                value: 0
46      0       0       0,0             0,0     0               0x00000001
  formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 0
        17 FB_ID:
                flags: object
                value: 0
        18 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        20 CRTC_ID:
                flags: object
                value: 0
        13 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        14 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        15 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 0
        16 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 0
        9 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        10 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        11 SRC_W:
                flags: range
                values: 0 4294967295
                value: 0
        12 SRC_H:
                flags: range
                values: 0 4294967295
                value: 0
        47 zpos:
                flags: range
                values: 0 3
                value: 0
        48 COLOR_ENCODING:
                flags: enum
                enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                value: 0
        49 COLOR_RANGE:
                flags: enum
                enums: YCbCr limited range=0 YCbCr full range=1
                value: 0
        50 alpha:
                flags: range
                values: 0 65535
                value: 65535
        51 pixel blend mode:
                flags: enum
                enums: Pre-multiplied=0 Coverage=1
                value: 0
52      0       0       0,0             0,0     0               0x00000001
  formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 0
        17 FB_ID:
                flags: object
                value: 0
        18 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        20 CRTC_ID:
                flags: object
                value: 0
        13 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        14 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        15 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 0
        16 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 0
        9 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        10 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        11 SRC_W:
                flags: range
                values: 0 4294967295
                value: 0
        12 SRC_H:
                flags: range
                values: 0 4294967295
                value: 0
        53 zpos:
                flags: range
                values: 0 3
                value: 0
        54 COLOR_ENCODING:
                flags: enum
                enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                value: 0
        55 COLOR_RANGE:
                flags: enum
                enums: YCbCr limited range=0 YCbCr full range=1
                value: 0
        56 alpha:
                flags: range
                values: 0 65535
                value: 65535
        57 pixel blend mode:
                flags: enum
                enums: Pre-multiplied=0 Coverage=1
                value: 0

Frame buffers:
id      size    pitch

root@j7-evm:~# [  133.833091] Initializing XFRM netlink socket
[  135.609719] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[  135.626935] Bridge firewalling registered
[  136.453514] process 'docker/tmp/qemu-check519628102/check' started with executable stack

    Thanks for the feedback.

     the log file for modetest is attached.

    I check the post, and it looks i am in his shoes.

    He also just gets DSI clock output and no DSI data output.

    BR,

    Richard

  • 0 in reply to Richard Hu
    TI__Guru**** 475245 points

    Hi Richard,

    Can you also run kmstest command and see if there is anything on the output?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Guru**** 475245 points

    Also please see output with below command. This should display some test pattern on the actual display.

    modetest -M tidss -s 39@37:1280x800

    Also please confirm if two items mentioned on below link are taken care. 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1159173/tda4vm-tda4vm-can-not-output-dsi-frequency-signal-on-linux/4364549#4364549

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 450 points

    Fullscreen modetest_-M_tidss_on_custom_tda4vm_20221013.txt Download 
    root@j7-evm:~# systemctl stop weston
root@j7-evm:~# [  133.543188] Initializing XFRM netlink socket
[  135.508853] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[  135.526017] Bridge firewalling registered
[  136.613944] process 'docker/tmp/qemu-check435078115/check' started with executable stack

root@j7-evm:~# kmstest
[  286.672230]
[  286.672230] --->panel_simple_get_non_edid_modes, start
[  286.679133]
[  286.679133] --->panel_simple_get_non_edid_modes, panel_simple_get_display_modes
[  286.688178]
[  286.688178] --->panel_simple_get_non_edid_modes, panel->desc->bpc = 8
[  286.696351]
[  286.696351] --->panel_simple_get_non_edid_modes, panel->desc->size.width = 161
[  286.705292]
[  286.705292] --->panel_simple_get_non_edid_modes, panel->desc->size.height = 243
[  286.714321]
[  286.714321] --->panel_simple_get_non_edid_modes, drm_display_info_set_bus_formats
[  286.723527]
[  286.723527] --->panel_simple_get_non_edid_modes, finish
[  286.730485]
[  286.730485] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_mode_valid, Line:251
[  286.742551]
[  286.742551] --->cdns_dsi_check_conf - start
[  286.748372]
[  286.748372] --->cdns_dsi_check_conf - cdns_dsi_mode2cfg
[  286.755234]
[  286.755234] --->cdns_dsi_check_conf - phy_mipi_dphy_get_default_config
[  286.763400]
[  286.763400] --->cdns_dsi_adjust_phy_config - cdns_dsi_adjust_phy_config
[  286.771649]
[  286.771649] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_adjust_phy_config, Line:129
[  286.783711]
[  286.783711] --->cdns_dsi_adjust_phy_config, lane number: 4
[  286.790919]
[  286.790919] --->cdns_dsi_adjust_phy_config - phy_validate
[  286.797968]
[  286.797968] --->cdns_dsi_adjust_phy_config - mode_to_dpi_hfp
[  286.805269]
[  286.805269] --->cdns_dsi_adjust_phy_config - done
[  286.814866] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.820553] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.826057] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.831556] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.838253] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.843767] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.849255] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.855850] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.861416] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
[  286.866897] tidss 4a00000.dss: CRTC2 SYNC LOST: (irq 8000)
Connector 0/@39: DSI-1[  286.884174]
[  286.884174] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_disable, Line:289

  Crtc 0/@37: 1280x800 67.000 1280/48/32/80/? 800/3/6/14/? 57 [  286.897735] ------> cdns_dsi_j721e_disable - start
(56.53) 0 0x48
  Plane 0/@31: 0,0-1280x800
    Fb 59 1280x800-[  286.908222]
[  286.908222] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_post_disable, Line:309
XR24
[  286.927371] tidss 4a00000.dss: vp2: Clock rate 600000000 differs over 5% from requested 67000000
[  286.936599]
[  286.936599] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_pre_enable, Line:532
[  286.949153]
[  286.949153] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_hs_init, Line:319
[  286.960379]
[  286.960379] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_enable, Line:397
[  286.972103] ------> cdns_dsi_j721e_enable - start
[  286.976974]
[  286.976974] --->cdns_dsi_check_conf - start
[  286.982796]
[  286.982796] --->cdns_dsi_check_conf - cdns_dsi_mode2cfg
[  286.989658]
[  286.989658] --->cdns_dsi_check_conf - phy_mipi_dphy_get_default_config
[  286.997820]
[  286.997820] --->cdns_dsi_adjust_phy_config - cdns_dsi_adjust_phy_config
[  287.006071]
[  287.006071] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_adjust_phy_config, Line:129
[  287.018132]
[  287.018132] --->cdns_dsi_adjust_phy_config, lane number: 4
[  287.025342]
[  287.025342] --->cdns_dsi_adjust_phy_config - phy_validate
[  287.032381]
[  287.032381] --->cdns_dsi_adjust_phy_config - mode_to_dpi_hfp
[  287.039674]
[  287.039674] --->cdns_dsi_adjust_phy_config - done
[  287.046016]
[  287.046016] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_hs_init, Line:319
press enter to exit

root@j7-evm:~# modetest -M tidss -s 39@37:1280x800
[  327.153307]
[  327.153307] --->panel_simple_get_non_edid_modes, start
[  327.160225]
[  327.160225] --->panel_simple_get_non_edid_modes, panel_simple_get_display_modes
[  327.169290]
[  327.169290] --->panel_simple_get_non_edid_modes, panel->desc->bpc = 8
[  327.177456]
[  327.177456] --->panel_simple_get_non_edid_modes, panel->desc->size.width = 161
[  327.186397]
[  327.186397] --->panel_simple_get_non_edid_modes, panel->desc->size.height = 243
[  327.195424]
[  327.195424] --->panel_simple_get_non_edid_modes, drm_display_info_set_bus_formats
[  327.204630]
[  327.204630] --->panel_simple_get_non_edid_modes, finish
[  327.211587]
[  327.211587] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_bridge_mode_valid, Line:251
[  327.223650]
[  327.223650] --->cdns_dsi_check_conf - start
[  327.229474]
[  327.229474] --->cdns_dsi_check_conf - cdns_dsi_mode2cfg
[  327.236336]
[  327.236336] --->cdns_dsi_check_conf - phy_mipi_dphy_get_default_config
[  327.244499]
[  327.244499] --->cdns_dsi_adjust_phy_config - cdns_dsi_adjust_phy_config
[  327.252752]
[  327.252752] --->File:drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c, Function:cdns_dsi_adjust_phy_config, Line:129
[  327.264814]
[  327.264814] --->cdns_dsi_adjust_phy_config, lane number: 4
[  327.272025]
[  327.272025] --->cdns_dsi_adjust_phy_config - phy_validate
[  327.279071]
[  327.279071] --->cdns_dsi_adjust_phy_config - mode_to_dpi_hfp
[  327.286375]
[  327.286375] --->cdns_dsi_adjust_phy_config - done
setting mode 1280x800-56.53Hz@XR24 on connectors 39, crtc 37

    The test command result is attached.

    1. I don't see any error message except "tidss 4a00000.dss: vp2: Clock rate 600000000 differs over 5% from requested 6700000"

    2. I can see DSI clock output on scope in the begainning. But after i issue "kmstest", the DSI clock stops to output.

    3. Weston should already output wayland desktop on the screen. kmstest just outputs specific pattern for checking display size and color.

    BR,

    Richard

  • 0 in reply to Brijesh Jadav
    Intellectual 511 points

    Brijesh, Ri,

    We've implemented the DSS/DSI based on the reference for Beagleboard DTS prior to starting this e2e topic, so we should be good. Please review:

    1) For the dss port assignment:

    github.com/.../k3-j721e-rovy-4vm-vizionpanel-vl10112880.dts

    2) For dphy2 clock assignment, refer to:

    github.com/.../k3-j721e-rovy-4vm-vizionpanel-vl10112880.dts

  • 0 in reply to Richard Hu
    TI__Expert 5145 points

    Hi, Richard

    I saw the message follow you mention before about "item3"

    3. Weston should already output wayland desktop on the screen. kmstest just outputs specific pattern for checking display size and color.

    Base on your case, a little bit curious, 

    so you can output screen form "DSI TX" ?

    just a check

    Many Thanks

    Gibbs

  • 0 in reply to Gibbs Shih
    Intellectual 450 points

    I'm sorry for the misunderstanding.

    I can't output screen from "DSI TX", because there is no DSI data signal output from TDA4VM.

    What i mean in item 3 is "weston already utilizes kms to render something. It should no need to use kmstest to render. it should not be a reason to cause no display output if i don't issue kmstest command."

    BR,

    Richard

  • 0 in reply to Brijesh Jadav
    Intellectual 450 points

    Because the DSI controller is configured to work at continuous mode.

    So even there is no data, it keeps outputting DSI clock.(It looks DSI controller is activated correctly.)

    I agree with what you say.

    It's possible that DSS doesn't output data stream to DSI controller.

    But how can i check and validate it?

    Thanks~!!!

    BR,

    Richard

  • 0 in reply to Richard Hu
    TI__Expert 5145 points

    Hi, Richard

    I am not sure this is an useful information

    I am studying TVG generator, it may make sure DSI+D PHY works well first

    for you reference.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1159173/tda4vm-tda4vm-can-not-output-dsi-frequency-signal-on-linux

    Gibbs

  • 0 in reply to Gibbs Shih
    Intellectual 450 points

    There is limited information about DSI block in TRM, i don't find any description about DSI register table.

    Is there any other document with DSI details?

    Thanks~

    BR,

    Richard

  • 0 in reply to Gibbs Shih
    Intellectual 450 points

    Thanks! I didn't notice register table is in another pdf...

  • 0 in reply to Richard Hu
    Intellectual 450 points

    I try to dump DSI status register and get some information:

    root@j7-evm:~# devmem2 0x0480002C
    /dev/mem opened.
    Memory mapped at address 0xffff80970000.
    Read at address  0x0480002C (0xffff8097002c): 0x000402A6

    It indicates only clk lane is in HS mode, and 4 data lanes are in idle state.

    It matches the result i see on scope.

    root@j7-evm:~# devmem2 0x04800024
    /dev/mem opened.
    Memory mapped at address 0xffffa5437000.
    Read at address  0x04800024 (0xffffa5437024): 0x0000003F

    It indicates clk lane, and 4 data lanes are ready.

    root@j7-evm:~# devmem2 0x048000F0
    /dev/mem opened.
    Memory mapped at address 0xffffbd858000.
    Read at address  0x048000F0 (0xffffbd8580f0): 0x00000004

    It indicates 'missing HSYNC'. Not sure how it happens.

    I see interrupt count of 'tidss' keeps increasing.
    root@j7-evm:~# cat /proc/interrupts | grep -i "dsi\|dss"
    41:          0          0     GICv3 632 Level     4800000.dsi
    42:       1286          0     GICv3 634 Level     tidss

    It indicates tidss is active!?

    But after i excute 'kmstest'. DSI status register shows as below:

    root@j7-evm:~# devmem2 0x0480002C
    /dev/mem opened.
    Memory mapped at address 0xffff86c74000.
    Read at address  0x0480002C (0xffff86c7402c): 0x00000000
    root@j7-evm:~# devmem2 0x04800024
    /dev/mem opened.
    Memory mapped at address 0xffff920b5000.
    Read at address  0x04800024 (0xffff920b5024): 0x00000001
    root@j7-evm:~# devmem2 0x048000F0
    /dev/mem opened.
    Memory mapped at address 0xffff89a04000.
    Read at address  0x048000F0 (0xffff89a040f0): 0x00000000

    It looks clock and data lanes are not in ready state yet!?

    BR,

    Richard

  • 0 in reply to Richard Hu
    TI__Guru**** 475245 points

    Hi Richard,

    I think you are now able to get some valid data from DSI after applying patches from Rohit, so let us know if we can close this ticket.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 511 points

    We can close this ticket. Thanks!