TMS320C6657: DDR3 configuration of the RBL or IBL for booting custom hardware

Brads,

Questions : 

The next step is to modify the IBL/RBL configurations to use these changes.  We are attempting to emulate the EVMs boot characteristics. (i.e. load the IBL from I2C EERPOM and the application from SPI FLASH.)  However, we are struggling to determine where/how to accomplish this task.

• Are there any documentation/application notes/instructions/examples that show where/how to modify/configure the IBL to properly configure the DDR3 interface before loading the application?
• Is it possible to load from SPI Flash directly with the RBL? (i.e. boot the processor directly from the SPI FLASH.)  If possible, are there any documentation/application notes/instructions/examples that show where/how to modify/configure the RBL to properly configure the DDR3 interface before loading the application?

Answers:

1. Yes, it is possible to modify the IBL. PLease visit here, to modify and re-build the IBL.

4.d) How to build the IBL –

2. I guess your question is Booting from SPI WITHOUT IBL. 

Yes, that is also possible.  https://www.ti.com/lit/an/spracn2/spracn2.pdf

Page no:  2 

2 Direct Boot Examples (without IBL) The TI C66xx EVMs always implement an Intermediate bootloader after power on reset. The FPGA firmware on the EVM redirects the core to the IBL flashed on the EEPROM and then directs it to the desired boot mode. However, in custom designs, it has been observed that adding an additional EEPROM for implementing the IBL may not be practical due to cost and size reasons. The C667x PG 2.0 silicon has the PLL lock up issue fixed and no longer requires an implementation of an IBL on custom boards; the C665x PG 1.0 silicon does not have the PLL lock up issue, so it also does not require an implementation of an IBL on custom boards. In order to demonstrate that the hardware can be booted directly from the ROM bootloader without the IBL, some examples were created that can be used to validate this flow on the EVM hardware.

The two examples described below are for SPI boot on C6678 and NAND boot on C6657. Each of the examples have a ReadMe.txt or document that walks users through the processing of creating these boot images.

• C6678 EVM SPI boot example

• C6657 EVM SPI boot example with DDR initialization

• C6657 EVM NAND boot example

Please note that the links to the "C6657 EVM SPI boot example" seems to be broken. Let me search and upload here, soon  

Regards

Shankari G

Thank you for the quick response.  I have been looking through the code in the C:\ti\pdk_c665x_2_0_16\packages\ti\boot\ibl directory.  However, since this IBL supports multiple processors and is not a CCS project that is openable with the IDE.  I am getting lost to determining how the IBL's flow and where to make the necessary changes to support by custom hardware.  Also, I am not sure that the IBL would need to change.

1) Is there a document that explains the IBL's operation?

2) Am I looking in the right place?  (i.e. do changes need to be made with the IBL to support the different DDR3 memory for my system.

3) Where can I find the example code/project referred to in your response 

Shankari G said:

C6657 EVM SPI boot example with DDR initialization

Thanks,

Brad

Brad,

I can help you on the following ( if your requirement is to boot the app along with IBL.... ) 

1. How to build IBL.

2. How to flash the IBL into the EEPROm

3. How to flash the app binary into the SPI-NOR.

---

As I already mentioned, the link to the example project for "C6657 EVM SPI boot example with DDR initialization" ( without IBL ) was broken.

I will update you soon on the link, where we can download the source of SPI boot example(without IBL )

--

Let me know your choice, so that I can guide you in that direction.

With IBL or Without IBL?

Regards

Shankari G

Our custom hardware replicated the configuration of the EVM with an I2C EEPROM, SPI NOR FLASH and DDR3 memory. 

Our current objective is to get our custom hardware to boot from I2C EEPROM memory and load an application from the SPI NOR FLASH into the DDR3 memory.  To that end, my initial objective is to use the IBL.

As I see it the steps to modify and load the process are:

1. Modify the Code.
   Find in the code where to modify the DDR3 memory configurations that I need to modify to support my custom hardware.
   I have been looking but have not yet found where in the IBL's code base to make my changes for the DDR3 memory configuration.  Can you point me to the correct file where the DDR3 memory is configured?
2. Compile the IBL
   This can be done by following the links shown above "How to build the IBL –"
3. Load the "new" IBL into the hardware.
   This can be accomplished by following the instructions in the following link (with modifications for our custom hardware)
   https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057566/faq-tms320c6657-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary 

My stretch objective would be to accomplish the loading of the application directly from the SPI NOR FLASH.  As you stated in your previous remarks the link to the code showing how loading the processor directly from the SPI FLASH's link is broken.  I would like to review this code to see how I could implement this boot mode in the future. 

In summary, my questions are:

1. Where in the IBL's code base are the configurations for the C6657's DDR3 memory initializations?
2. Where can I find the "C6657 EVM SPI boot example with DDR initialization"?

Thanks in advance for your assistance,

Brad

Brads said: 

---------------

In summary, my questions are:

1. Where in the IBL's code base are the configurations for the C6657's DDR3 memory initializations?
2. Where can I find the "C6657 EVM SPI boot example with DDR initialization"?

--

Answers:

1. Let me look at it and get back by EOD.

2. I have already forwarded to the concern department that the link to download the example is broken. We may have to wait until they reply.

Regards

Shankari G

In looking at the example code for the direct SPI boot, it looks like the user needs to configure the emif4Cfg structure with the register configurations needed for their hardware.  I am translating a working configuration (from a GEL file) to fill out this structure.  However, I do not understand where some of the values in the structure are to come from.  At the bottom of this post is my current configuration.

Questions:

1. Where was the value, (3,      /* pllPrediv          */), is derived from?
2. My working GEL file has values for DataX_WRLVL_INT_RATIO and DataX_GTLVL_INIT_RATIO.  Where are these values supposed to be added to the configuration structure?
3. At the end of the structure there are some values that do not have any comments. (i.e. 0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A....)
   1. What do these values represent/do?  

Thanks,

Brad

const BOOT_EMIF4_TBL_T  emif4Cfg =  {
 
     BOOT_EMIF4_ENABLE_MSW_pllCtl               | \
     BOOT_EMIF4_ENABLE_MSW_sdRamTiming1         | \
     BOOT_EMIF4_ENABLE_MSW_sdRamTiming2         | \
     BOOT_EMIF4_ENABLE_MSW_sdRamTiming3         | \
     BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1           | \
     BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
     BOOT_EMIF4_ENABLE_MSW_sdRamConfig,
 
     BOOT_EMIF_ENABLE_SLSW_config0  | \
     BOOT_EMIF_ENABLE_SLSW_config6  | \
     BOOT_EMIF_ENABLE_SLSW_config7  | \
     BOOT_EMIF_ENABLE_SLSW_config8  | \
     BOOT_EMIF_ENABLE_SLSW_config9  | \
     BOOT_EMIF_ENABLE_SLSW_config10 | \
     BOOT_EMIF_ENABLE_SLSW_config18 | \
     BOOT_EMIF_ENABLE_SLSW_config19 | \
     BOOT_EMIF_ENABLE_SLSW_config20 | \
     BOOT_EMIF_ENABLE_SLSW_config22 | \
     BOOT_EMIF_ENABLE_SLSW_config12 | \
     BOOT_EMIF_ENABLE_SLSW_config23 | \
     BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
     0,      /* Config select lsw  */
    
     3,      /* pllPrediv          */
     79,     //(originalvalue)40,     /* pllMult    */
     2,      //(originalvalue)2,      /* pllPostDiv */
 
     0x63026AB2,  //(originalvalue)0x62477AB2,  /* sdRamConfig */
     0,           /* sdRamConfig2,          dont care*/
     0x00001458,  //(originalvalue)0x0000144F,  /* sdRamRefreshCtl  */
     0x1113783C,  //(originalvalue)0x1333780C,  /* sdRamTiming1 */
     0x30B37FE3,  //(originalvalue)0x30717FE3,  /* sdRamTiming2 */
     0x559F8ADF,  //(originalvalue)0x559F86AF,  /* sdRamTiming3 */
 
     0,           /* lpDdrNvmTiming,        dont care */
     0,           /* powerManageCtl,        dont care */
     0,           /* iODFTTestLogic,        dont care */
     0,           /* performCountCfg,       dont care */
     0,           /* performCountMstRegSel, dont care */
     0,           /* readIdleCtl,           dont care */
     0,           /* sysVbusmIntEnSet,      dont care */
     0x70074c1f,  /* sdRamOutImpdedCalCfg,  dont care */
     0,           /* tempAlterCfg,          dont care */
 
     0x0010010F,  /* ddrPhyCtl1 */
 
     0,           /* ddrPhyCtl2,            dont care */
     0,           /* priClassSvceMap,       dont care */
     0,           /* mstId2ClsSvce1Map,     dont care */
     0,           /* mstId2ClsSvce2Map,     dont care */
     0,           /* eccCtl,                dont care */
     0,           /* eccRange1,             dont care */
     0,           /* eccRange2,             dont care */
     0,           /* rdWrtExcThresh,        dont care */
 
     0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
     0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
     0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
     0, 0, 0, 0, 0, 0, 0, 0,
    
     0, 0, 0, 0, 0, 0, 0, 0,
     0, 0, 0, 0, 0, 0, 0, 0,
     0, 0, 0, 0, 0, 0, 0, 0,
     0, 0, 0, 0, 0, 0, 0, 0
 };

Brad,

Festive season here.

Sorry for the delay.

Let me look at it and get back.

Regards

Shankari G

BradS said:

At the end of the structure there are some values that do not have any comments. (i.e. 0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A....)

1. What do these values represent/do? 

Those 64 are the values of  chipConfig " UINT32 chipConfig[64];"  in  typedef struct bootEmif4Tbl_s in tiboot.h

For the values of  " DDR3 Configuration 0 Register (DDR3_CONFIG_0) to DDR3 Configuration 60 Register (DDR3_CONFIG_60), they maintained in the array, UINT32 chipConfig[64];

For more details refer to the "Keystone Architecture DDR3 Memory Controller User's Guide" - https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf

Page no: 88 to 117, sections : 4.31 to 4.89

------------------------------

typedef struct bootEmif4Tbl_s {

UINT32 configSelect_msw; /* Bit map defining which registers to set */
UINT32 configSelect_slsw; /* Bit map defining which registers to set */
UINT32 configSelect_lsw; /* Bit map defining which registers to set */

UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;

UINT32 sdRamConfig; /* Controlled by bit 1 of configSelect_msw */
UINT32 sdRamConfig2; /* Bit 2 */
UINT32 sdRamRefreshCtl; /* Bit 3 */
UINT32 sdRamTiming1; /* Bit 4 */
UINT32 sdRamTiming2; /* Bit 5 */
UINT32 sdRamTiming3; /* Bit 6 */
UINT32 lpDdrNvmTiming; /* Bit 7 */
UINT32 powerManageCtl; /* Bit 8 */
UINT32 iODFTTestLogic; /* Bit 9 */
UINT32 performCountCfg; /* Bit 10 */
UINT32 performCountMstRegSel; /* Bit 11 */
UINT32 readIdleCtl; /* Bit 12 */
UINT32 sysVbusmIntEnSet; /* Bit 13 */
UINT32 sdRamOutImpdedCalCfg; /* Bit 14 */
UINT32 tempAlterCfg; /* Bit 15 */
UINT32 ddrPhyCtl1; /* Bit 16 */
UINT32 ddrPhyCtl2; /* Bit 17 */
UINT32 priClassSvceMap; /* Bit 18 */
UINT32 mstId2ClsSvce1Map; /* Bit 19 */
UINT32 mstId2ClsSvce2Map; /* Bit 20 */
UINT32 eccCtl; /* Bit 21 */
UINT32 eccRange1; /* Bit 22 */
UINT32 eccRange2; /* Bit 23 */
UINT32 rdWrtExcThresh; /* Bit 24 */

UINT32 chipConfig[64];

} BOOT_EMIF4_TBL_T;

-----

BradS said:

My working GEL file has values for DataX_WRLVL_INT_RATIO and DataX_GTLVL_INIT_RATIO.  Where are these values supposed to be added to the configuration structure?

Please upload the gel files, you use. Because in the standard TI-offered gel files, like evmc6657l.gel, I could not find "DataX_WRLVL_INT_RATIO"

----

BradS said:

Where was the value, (3,      /* pllPrediv          */), is derived from?

That is the periperal clock derived from the system clock.

Please refer to the 

1.https://www.ti.com/lit/ds/symlink/tms320c6657.pdf page no :83 - 85 - section : 6.6.1 Main PLL Controller Device-Specific Information 6.6.1.1 Internal Clocks and Maximum Operating Frequencies

SYSCLK3: 1/2-rate clock used to clock the MSMC, HyperLink, and DDR EMIF

 https://www.ti.com/lit/ug/sprugv2i/sprugv2i.pdf 

Regards

Shankari G

Thank you for your response.  

The reference to the SPRUGV8E clears up several of my questions and presents a few more.

1. Your response clears up the definition of the additional registers.
2. My question regards to DataX_WRLVL_INT_RATIO and DataX_GTLVL_INIT_RATIO, This was an attempt to generalize a reference to Data0_WRLVL_INT_RATIO, Data1_WRLVL_INT_RATIO,...  This question is answered by SPRUGV8E.  These values are set in the chipConfig registers.
3. The clock rate to the DDR PLL is 1/2 the system clock rate.  This raises a question about the DDR3 example contained in  2781.C6657_directROM_Boot_example.zip.  In this example the pllPrediv is set to 3, so that implies that the clock provided to the DDR memory is 1/3 of the system clock rate.  Is this example wrong?  i.e. should the pllPrediv be set to 2?
4. I am using definitions in SPRUGV8E to decode the direct boot example provided by TI.  DDR3_CONFIG_0 is getting set to 0x87A0047F.  The document states that the user should not write to these bits.  Why is TI's example writing to these reserved bits?
5. Same question for DDR3_CONFIG_12.  The register is getting set to 0xAF00002, most of these bits are in reserved fields. Why is TI's example writing to these reserved bits?
6. In correlating SPRUGV8E to the example.. The example is setting values of zero for chipConfig 2 through 5, which are the reg_phy_wrlvl_init_ratio registers for the C6657, and are setting values for chipConfig 6 through 9, which are also reg_phy_wrlvl_init_ratio values but are listed as NA for the C6657.  Which documentation is correct, the example code or the document?
7. Same question as 6 for chipConfig 14 to 21 (reg_phy_gatelvl_init_ratio) registers.  The example is writing to the NA registers.  Which documentation is correct?
8. In looking at the direct boot example,  the sdRamOutImpdedCalCfg is configured for a value but the comment states that the value is a "dont care".  Does the user need to configure this value?  Is the value provided the value that needs to be set or is it truly a "don't care" register?
9. I am not an expert on DDR3 or the TI EMIF,  Why does the example state that most of the configuration registers are "dont care" ?

Thanks,

Brad

Brad,

Go to KeyStone I DDR3 Initialization guide - https://www.ti.com/lit/an/sprabl2e/sprabl2e.pdf

and download  http://www.ti.com/lit/zip/sprabl2. at page no:1.

For custom board, we have to use the following spread sheets for DDR3 register calculations and configurations.

--

5164.DDR3 PHY Calc v11.xlsx

5417.DDR3 Register Calc v4.xlsx

Some sample values here for the device used is K4B2G1646C (1333) - DRAM CHIP

For custom board, you have to use these spread sheets which-in-turn will automatically derive you the DDR3 register values to be used in the gel file and  software source files.... 

Some sample values here for the device used is K4B2G1646C (1333) - DRAM CHIP

---

Since the same code base is used for the series of devices, such as C6657, C6678, keystone -II devices susch as K2E, K2H etc, sometimes the comments in the source code may not be updated. And also please note that it is a 7 years old code.

It is better to stick to the documentation.

--

If C6657 EVM is available, try the following.....

At the first hand, try out the direct-boot-example ( just the binary ) works on the C6657 EVM using the Readme.txt------> located at "C6657_directROM_Boot_example.zip\C6657\SPIboot_ddr\docs"

If successful, as a next step, rebuild the binary and try loading and checking using the "SPIboot_with_DDR_UserGuide.docx"---->located at C6657_directROM_Boot_example\C6657\SPIboot_ddr\docs

if successful, then we shall go into deeper details...digging more on the chipConfig values.....

Please share your thoughts....

--

General note: You will find all the necessary technical documents under the product folder - https://www.ti.com/product/TMS320C6657#tech-docs

"KeyStone I DDR3 Initialization" guide is one among the 82 technical documentation.

--

I have exclusively created one FAQ page here on DDR3 register calculation: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1096375/faq-66ak2e05-how-to-calculate-the-ddr3-interface-registers-for-keystone-ii-devices-and-test-debug-on-keystone-ii-evm

But this is for Keystone - II ( two - K2H and K2E ) devices. But the procedure remains same for keystone ( one devices - C6657 and C6678 ) except the spreadsheets have to be downloaded from "KeyStone I DDR3 Initialization guide".... 

Regards

Shankari G

I appreciate your understanding as I work through issues of finding and processing the information TI provides.

I understand that the example is old and developed as common examples for many processors and errors do find their way into examples.  Since I do not know very much about this subject I was hoping that the examples were correct enough to guide me through my initial development. 

I seems like I need to re-start the discussion and work from the simple to the complex.  To do this I have worked on an example should be operational on both the EVM and my custom hardware.  The end goal here is to be able to boot the processor from the SPI NOR flash and have the RBL load the code into the DDR3 memory and initiate the program.  To this end there are a few steps that need to be covered. 

• Connect to the Custom Hardware
• Load the SPI NOR memory with data.
• Configure the RBL to boot from the SPI NOR memory 

To work through this below I have detailed my current steps to create a verifiably good SPI NOR image and the processes I used to load that image onto the custom hardware.

1. Created a custom GEL file to support the custom hardware (ie. DDR3 memory).
   1. This is a copy of the evmc6657l.gel with modification to the DDR3 configuration based upon our board and memories.  
   2. The GEL file modifications were made based upon the DDR3 PHY calc v11.xlsx and DDR3 Registers v4.xlsx spreadsheets from http://www.ti.com/lit/zip/sprabl2.
   3. Additional debug statements were added into the file to report the DEVSTAT and Bootmode upon connection to the processor.
   4. With these changes the GEL file properly debugger is able to connect to the custom hardware, load code into DDR3 memory and execute.saratoga_1333.gel
2. SPI Direct boot code
   1. I have downloaded the example code, 2781.C6657_directROM_Boot_example.zip, 
   2. Added code to this example to prove that the code loaded and is executing.  The only modification was to the main function to turn the GPIO21/UARTTXD into a GPIO line and perpetually toggle this line at a nominal rate. 

      void main(void)
      {
          volatile uint32_t *BOOT_COMPLETE        = (volatile uint32_t *)0x0262013C;
          volatile uint32_t *PIN_CONTROL_0        = (volatile uint32_t *)0x02620580;
          volatile uint32_t *GPIO_C6657_DIR       = (volatile uint32_t *)(0x02320000 + 0x10);
          volatile uint32_t *GPIO_C6657_OUT_DATA  = (volatile uint32_t *)(0x02320000 + 0x14);
          uint32_t loop_cnt = 0;
      
          *BOOT_COMPLETE  = 0x00000003;// Set BootComplete 0 and 1
          *PIN_CONTROL_0  = 0x00200000;
          *GPIO_C6657_DIR = 0xFFDFFFFF;// GPIO21 Output
          for (loop_cnt = 0; loop_cnt < 0x0FFFFFFF; loop_cnt++) {
              uint32_t x;
              for (x=0; x<0x1fffffe;x++) {
                  *GPIO_C6657_OUT_DATA = 0x00200000;// GPIO21 High
              }
      
              for (x=0; x<0x1fffffe;x++) {
                  *GPIO_C6657_OUT_DATA = 0x0; // GPIO21 Low
              }
          }
      //    asm("	IDLE");
      }

   3. Compiled this code following the instructions in the directROM_Boot_example documentation.
   4. Execute the example code on the EVM.
      1. Loaded the code compiled code to the TMDS6657LS EVM.  Following the instructions in the example documentation.
      2. Configured the EVM for SPI Boot SW3 {pin 0 - pin8) = 10110000 (0-ON, 1-OFF) SW5(pin0 - pin8) = 00100000.
      3. Rebooted the EVM.
      4. After boot the EVM's GPIO21 toggles.
3. Additional Changes to the SPI Direct boot code
   1. Changed the rate at which the GPIO toggles
   2. I changed the spiboot.cmd file to add a new MEMORY definition, L2_DATA   :  origin = 0x800000,   length = 0xff000, and directed all of the defined SECTIONS to point to this internal memory.
      

      spiboot.obj
      
      -c
      -a
      -stack 0x400
      
      MEMORY
      {
          DDR_CFG   :  origin = 0x8ffd20, length = 0x180
      	L2MAGIC   :  origin = 0x8ffffc, length = 0x4
      
      	DDR       :  origin = 0x80000000, length = 0x2000
      	L2_DATA   :  origin = 0x800000,   length = 0xff000
      }
      
      
      SECTIONS
      {
          .emif4Cfg > DDR_CFG
      
      	.stack > L2_DATA
      	.msmc  > L2_DATA
      	.data  > L2_DATA
      	.far   > L2_DATA
      	.text  > L2_DATA
      	.const > L2_DATA
      	.cinit > L2_DATA
      	.lmagic > L2MAGIC
      	
      
      }

   3. Compiled this code following the instructions in the directROM_Boot_example documentation.
   4. Execute the example code on the EVM as described above in 2.d.
   5. The GPIO toggled at the new data rate.
4. Verify that the custom hardware responds to the code as expected.
   1. Added the code changes to the top of the main() function in a project that runs on the custom hardware.
   2. Compile and load the code to the custom hardware.
   3. Run the code and validate that the GPIO21/UARTTXD line toggles as directed by the code.
5. Run the internal RAM example on the Custom Hardware.
   1. The Custom Hardware is very similar to he EVM 
      1. A similar SPI memory is used (ie. larger due to availability)
      2. The SPI memory CS is the same as the EVM.  The other SPI CS goes off board (i.e. not used/connected)
      3. The same input clock frequency to the processor is used.
      4. The bootmode pins are configurable.  The mode pins are configurable by switches the other pins by resistor pull ups and downs (install/remove)
   2. Load the code into the custom hardware
      
      1. The bootmode pins of the C6657 are set to No Boot.  (The GEL file reports the current DevStat register value, C66xx_0: GEL Output: DEVSTAT 0x00018401 Bootmode = 0x00000000)
      2. Using the modified GEL file a connection is established between the XDS200 development pod and the custom hardware.
      3. The NOR Writer is loaded from the 2781.C6657_directROM_Boot_example\C6657\SPIboot_ddr\bin\flashwriter\norwriter_evm6657l.out
      4. The app.dat is loaded into DDR memory.
      5. The NOR Writer application is executed.
      6. The Console reports Success. 
         
   3. Changed the boot mode pins to SPI Boot. (Validated by connecting with the XDS200 and seeing what the DEVSTAT register is showing C66xx_0: GEL Output: DEVSTAT 0x0001840D Bootmode = 0x00000006.
   4. After cycling power on the custom board, GPIO21/UARTTXD does not toggle.

NOTE:  I believe that the code is be loading into the internal L2 Ram, so there should not be any issue with the setup of the DDR memory at this time.

• Since the bootmode pins are not set directly by the EVM user switches, I do not know for certain how the bootmode lines are configured during the EVM's SPI boot.  Can you confirm that my settings of the bootmode lines at startup are correct for SPI boot?
• Do you have any idea as to why the custom hardware does not boot?

While waiting for your answer, I will read/reread the DDR3 resources you have directed me towards and ask more questions after the unit can boot from SPI.

Thanks in advance for you assistance.

Brad

Brad,

Ok. Let me check all your steps.

Regards

Shankari G

Brad,

All your steps seems to be right.

How nicely, you summarized ....  Too good.

I am experimenting and validating your steps through the C6657 EVM , which  I have in hand.

Will let you know my results in a day or two.

Regards

Shankari G

Brad,

1. I have validated the direct boot example ( SPI-NOR with DDR using NOR writer)on C6657 EVM and could verify that the direct boot works successfully.

2. Let me post the steps with screenshots and videos tomorrow.

( I guess, you might have left this step - open the app.dat in ccs and edit the value at 0x1F offset as 00.  It will be 0x51. ) Other than that, all your steps should be correct

DIP switch settings you used are correct: 

SW3 {pin 0 - pin8) = 10110000 (0-ON, 1-OFF) SW5(pin0 - pin8) = 00100000. ( The same I used for ROM SPI boot  on C6657 EVM)

Regards

Shankari G

As I tried to explain in my last post, I was able to create two applications the EVM that can be loaded into the SPI NOR flash and were able to run properly.  This was validated by monitoring the TXD line (configured as a GPIO out) toggles between low and high voltages.  The first one loaded into external DDR3 memory and the second one loaded into internal L2_DATA memory. 

NOTE:  These applications were both validated as operational with the EVM hardware!!  (i.e. the GPIO line toggled)

THEREFORE, from this testing the creation of the application binary was proven to be built correctly!!!

Since my custom hardware is very, very similar to that of the EVM

1. Same manufacturer
2. Same family
3. Connected to the same pins of the DSP
4. The SPI NOR writer program reports success when loading the SPI memory. 

This along with the fact that the debugger is able to connect, load and debug code, my only conceivable issue would be that of something different with the BOOTMODE pins.

To this end let me explicitly restate my questions from the previous post.

1. What is the proper configuration of the bootmode pins [12..0]
   1. How the EVM boot works
      1. the FPGA sets the bootmode pins to boot from the I2C EEPROM. 
      2. The DSP boots the IBL from the EEPROM.
      3. The IBL then configures the DDR3 memory.
      4. The IBL then queries the FPGA for the user configured bootmode switches/settings.
      5. The IBL then modifies the DEVSTAT register (which contains the bootmode pins) for the user selected bootmode.  In this case it is SPI boot.
      6. Then the IBL calls the RBL as if it was called directly from the hardware.
      7. If this is not correct please correct this description!!!
   2. My question:  In order to replicate the EVM's SPI boot on my custom hardware, I need to confirm the value of the DEVSTAT register when the IBL calls the RBL. Would you please provide this value?
2. Do you have any idea as to why the custom hardware does not boot?
   1. Assuming you have worked with other customers that have had issues with getting the C6657 to boot from the SPI NOR flash. 
      1. Can you provide any information about issues other customers have had getting the C6657 to boot from the SPI.  (i.e. problems and resolutions to other customer's cases)
      2. Are there other subsystems in the C6657 that could cause issues with getting the processor to boot from the SPI?
      3. Do you have any troubleshooting guides that might help us determine why the processor is not booting from the SPI?
   2. Do you see any issues with the process I have been following for debugging the SPI boot issue.
   3. Would you need any additional information to assist in the debugging of the SPI boot of the C6657?

I have been working on attempting to work with you for over three weeks trying to solve this issue!!!! 

Since this processor will not boot from flash yet it is now impacting our product development.  A quick solution to this issue is needed!!!

NOTE: Our custom hardware also contains an I2C EEPROM (like the EVM).  If using this to boot the processor will get us there quicker, I am willing to switch to working on getting the C6657 to boot from I2C.  No matter what I need to get this processor to boot from non-volatile memory soon. 

Thanks in advance for your assistance.

Bard

Brad,

Now, your questions are on IBL?

So far, we are trying to do the boot directly without IBL right? . The Direct SPI-boot example will have the booting flow like :- RBL -->App on SPI-NOR --> Without IBL !.

--

1. RBL is ROM bootloader -- This cannot be modified.

2. IBL is Intermediate bootloader -- This is also known as secondary bootloader.

3. app.dat is the binary which gets flashed into non-volatile memory and gets executed.

Please note: - IBL never calls RBL. 

---

There are only two ways of booting.

1. RBL + IBL + app.bin 

2. RBL + app.dat --> Direct boot example.

---

For the first method,

1. RBL + IBL + app.bin - This is the only reliable document available : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057566/faq-tms320c6657-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary

2. RBL + app.dat --> Direct boot example --> yet to be posted by me as a FAQ.

Let me know which way/method you want to proceed ? 

--

The following are the documents on Boot loader and boot modes.

1. https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf - KeyStone Architecture Literature Number: SPRUGY5C July 2013 DSP Bootloader user guide

2. https://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#c66x

3. https://www.ti.com/lit/an/spracn2/spracn2.pdf - Boot loader FAQs.

---

Regards

Shankari G

Brad,

Now, your questions are on IBL?

So far, we are trying to do the boot directly without IBL right? . The Direct SPI-boot example will have the booting flow like :- RBL -->App on SPI-NOR --> Without IBL !.

--

1. RBL is ROM bootloader -- This cannot be modified.

2. IBL is Intermediate bootloader -- This is also known as secondary bootloader.

3. app.dat is the binary which gets flashed into non-volatile memory and gets executed.

Please note: - IBL never calls RBL.

RBL calls IBL and it cannot be vice versa.

---

There are only two ways of booting.

1. RBL + IBL + app.bin 

2. RBL + app.dat --> Direct boot example.

---

For the first method,

1. RBL + IBL + app.bin - This is the only reliable document available : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057566/faq-tms320c6657-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary

2. RBL + app.dat --> Direct boot example --> yet to be posted by me as a FAQ.

Let me know which way/method you want to proceed ? 

--

The following are the documents on Boot loader and boot modes.

1. https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf - KeyStone Architecture Literature Number: SPRUGY5C July 2013 DSP Bootloader user guide

2. https://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#c66x

3. https://www.ti.com/lit/an/spracn2/spracn2.pdf - Boot loader FAQs.

---

Regards

Shankari G

OK, I must have gotten my information wrong about the internal operation of the IBL.

You are correct in that our end goal (and what I have been working on to date) is to boot the C6657 directly from the SPI NOR flash WITHOUT the IBL.  I brought up the fact that we could also attempt to use the IBL because I seem to be getting nowhere with the direct boot method.

RBL+IBL+app.bin

I have previously read and replicated the IBL example on the EVM.  i.e. I have recompiled the IBL code and loaded it onto the EVM and was able to get this version of the IBL to boot the EVM.  However, this is all that the link shows.. t does not go into the issue with where and how to modify the IBL to work with custom hardware. (which is my need)

RBL+app.dat

I have worked through the documentation  2781.C6657_directROM_Boot_example.zip and have used it to create an application that was successfully loaded on the EVM.

However, neither of these examples talks about what the bootmode[12..0] pins are set to when the DSP is booted.

EVM Discussion

From what I have read about the EVM, the FPGA configures the bootmode pins of the C6657 to something ('it is unknown to me as to what the pins are set to") to cause the C6657 to boot from the I2C.  The IBL is previously loaded into the I2C EEPROM.  At this point the C6657 starts executing the IBL. The IBL configures the DDR memory and then queries the FPGA for the user configuration of the EVM's SW3 and SW5 settings.  Then based upon these configurations the IBL then configures for that boot mode and then loads the processor. 

What I want / need to know

To continue to debug my custom hardware I want to confirm that I have the bootmode pins are correctly configured for the SPI boot.  This is not directly address in the directROM_Boot_example.  The settings shown are for the EVM boot mode switch settings. 
What I would like to know is:

1. What should the bootmode pins[12..0] be set to to properly configure the RBL for SPI NOR booting?
2. For my understanding, what does the EVM FPGA set the bootmode pin[12..0] to when the C6657 is booted?  I believe these would be the setting for I2C boot.

Please answer these two questions in your next reply.

Thank you in advance, 

Brad

Brad,

BradS said:

To continue to debug my custom hardware I want to confirm that I have the bootmode pins are correctly configured for the SPI boot.  This is not directly address in the directROM_Boot_example.  The settings shown are for the EVM boot mode switch settings. 
What I would like to know is:

1. What should the bootmode pins[12..0] be set to to properly configure the RBL for SPI NOR booting?
2. For my understanding, what does the EVM FPGA set the bootmode pin[12..0] to when the C6657 is booted?  I believe these would be the setting for I2C boot.

====================

Answer for Question [1] :

====================

The value of DEVSTAT shows up the value : which indicates as SPI-boot.

Please look at the value of DEVSTAT register value in the memory browser window as : and if could map it with the data sheet, I could decode as SPI-BOOT.

In your custom board setup please check what value it shows up... 

Devstat value - 0x40D = 0100 0000 1101 = Decode with page no: 205 in the data sheet  https://www.ti.com/lit/ds/symlink/tms320c6657.pdf

====

1101 -

====

0th Bit  ---> Shows the status of whether the system is operating in Big Endian mode or Little Endian mode. •

value 0 = System is operating in Big Endian mode

Value 1 = System is operating in Little Endian mode

And hence, the .dat is the LE format - Little endian format- we built as "spirom_le_swap.dat"

----

Devstat - Bit [1:13] = BOOTMODE[12:0]  --- > 110 -- SPIBOOT ( Here the boot mode value in the devstat matches with both the boot mode and the SW3 switch 5432 as 0110 )

Devstat [1:3 ] = Boot mode [ 0:2 ]

Here the value is 110.

Devstat 1:3 = Boot mode 0:2

======================

Answer for Question [2] :

======================

https://www.einfochips.com/wp-content/uploads/2016/04/C6657-Lite-EVM_TechnicalReferenceManual.pdf

2.2 EVM Boot mode and Boot Configuration Switch Settings C6657 Lite EVM has three configuration switches SW3, SW5 and SW9 that contain 18 values latched when reset is released. This occurs when power is applied the board, after the user presses the FULL_RESET push button or after a POR reset is requested from the MMC. SW3, SW5 and SW9 determine general DSP configuration, Little or Big Endian mode and boot device selection, DSP boot device configuration, CorePac PLL setting and PCIe mode selection and enable. Please refer to Section 3.3 of this document for default switch setting and details of each switch. For more information on DSP supported Bootmode, refer TMS320C6657 Datasheet and C66x Boot Loader User Guide.

As the EVM is the make of the Advantech, for other docs, refer to this website: https://www.einfochips.com/partnerships-and-alliances/device-partnerships/texas-instruments/tms320c6657-evm/ under "resources - column"

---

I understand your point.

Let us work one by one and more over one-option-at-a-time.

Will attempt few techniques in analysing or debugging on direct boot and then let us move into the RBL+IBL +app.

--

Let us check the following and narrow down one by one... ( When it comes to custom hardware, patience will play a key role for people like us..) 

1. The size of the direct boot example seems to be 25KB. what is the size of the .dat file which gets flashed on the NOR memory into the custom board.

2. What is the length value set during "load memory option" in the length in memory words section? 

3. Let me post the steps on what I validated as direct boot example.

And then, please try to repeat on both the EVM and the custom hardware and observe the behaviour. And then let us try to take it from there......

---

Regards

Shankari G

Starting with your list of questions...

1. The size of the direct boot example seems to be 25KB. what is the size of the .dat file which gets flashed on the NOR memory into the custom board.
   The file I am loading is a minor modification to the SPI Direct boot example. 

   /* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
    *
    *
    *  Redistribution and use in source and binary forms, with or without
    *  modification, are permitted provided that the following conditions
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the
    *    documentation and/or other materials provided with the
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
   
   #include <stdio.h>
   #include <string.h>
   #include <stdint.h>
   #include "tiboot.h"
   #include "platform.h"
   
   #pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
   #ifdef BHS_CUSTOM_BOARD
   const BOOT_EMIF4_TBL_T  emif4Cfg =  {
   
       BOOT_EMIF4_ENABLE_MSW_pllCtl               | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming1         | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming2         | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming3         | \
       BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1           | \
       BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl      | \
        BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
       BOOT_EMIF4_ENABLE_MSW_sdRamConfig,
   
       BOOT_EMIF_ENABLE_SLSW_config0  | \
       BOOT_EMIF_ENABLE_SLSW_config6  | \
       BOOT_EMIF_ENABLE_SLSW_config7  | \
       BOOT_EMIF_ENABLE_SLSW_config8  | \
       BOOT_EMIF_ENABLE_SLSW_config9  | \
       BOOT_EMIF_ENABLE_SLSW_config10 | \
       BOOT_EMIF_ENABLE_SLSW_config18 | \
       BOOT_EMIF_ENABLE_SLSW_config19 | \
       BOOT_EMIF_ENABLE_SLSW_config20 | \
       BOOT_EMIF_ENABLE_SLSW_config22 | \
       BOOT_EMIF_ENABLE_SLSW_config12 | \
       BOOT_EMIF_ENABLE_SLSW_config23 | \
       BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
       0,      /* Config select lsw  */
       
       2,      //(originalvalue)3,      /* pllPrediv          */
       79,     //(originalvalue)40,     /* pllMult    */
       2,      //(originalvalue)2,      /* pllPostDiv */
   
       0x63026AB2,  //(originalvalue)0x62477AB2,  /* **sdRamConfig */
       0,           /* sdRamConfig2,          dont care*/
       0x00001458,  //(originalvalue)0x0000144F,  /* **sdRamRefreshCtl  */
       0x1113783C,  //(originalvalue)0x1333780C,  /* **sdRamTiming1 */
       0x30B37FE3,  //(originalvalue)0x30717FE3,  /* **sdRamTiming2 */
       0x559F8ADF,  //(originalvalue)0x559F86AF,  /* **sdRamTiming3 */
   
       0,           /* lpDdrNvmTiming,        dont care */
       0,           /* powerManageCtl,        dont care */
       0,           /* iODFTTestLogic,        dont care */
       0,           /* performCountCfg,       dont care */
       0,           /* performCountMstRegSel, dont care */
       0,           /* readIdleCtl,           dont care */
       0,           /* sysVbusmIntEnSet,      dont care */
       0x70074c1f,  /* sdRamOutImpdedCalCfg,  dont care */
       0,           /* tempAlterCfg,          dont care */
   
       0x0010010F,  /* **ddrPhyCtl1 */
   
       0,           /* ddrPhyCtl2,            dont care */
       0,           /* priClassSvceMap,       dont care */
       0,           /* mstId2ClsSvce1Map,     dont care */
       0,           /* mstId2ClsSvce2Map,     dont care */
       0,           /* eccCtl,                dont care */
       0,           /* eccRange1,             dont care */
       0,           /* eccRange2,             dont care */
       0,           /* rdWrtExcThresh,        dont care */
   
       0x87A0047F,  /* **DDR3_CONFIG_0 [CMD_PHY_CTRL_SLAVE_RATIO and CMD_PHY_DLL_LOCK_DIFF] */
   	0,           /* DDR3_CONFIG_1 [PHY_DQ_OFFSET]*/
   	0x5A,        /* **DDR3_CONFIG_2 [DATA0_PHY_WRLVL_INIT_RATIO]*/
   	0x5B,        /* **DDR3_CONFIG_3 [DATA1_PHY_WRLVL_INIT_RATIO]*/
   	0x44,        /* **DDR3_CONFIG_4 [DATA2_PHY_WRLVL_INIT_RATIO]*/
   	0x44,        /* **DDR3_CONFIG_5 [DATA3_PHY_WRLVL_INIT_RATIO]*/
   	0,           /* **DDR3_CONFIG_6 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_7 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_8 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_9 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_10 [DATA8_PHY_WRLVL_INIT_RATIO]*/
   	0,           /* DDR3_CONFIG_11 [NA]*/
   	0x0800000,   /* **DDR3_CONFIG_12 [CMD_PHY_INVERT_CLKOUT & USE_RANK0_DELAYS]*/
   	0,           /* DDR3_CONFIG_13 [NA]*/
   	0x81,        /* **DDR3_CONFIG_14 [DATA0_PHY_GATELVL_INIT_RATIO]*/
   	0x80,        /* **DDR3_CONFIG_15 [DATA1_PHY_GATELVL_INIT_RATIO]*/
   	0x79,        /* **DDR3_CONFIG_16 [DATA2_PHY_GATELVL_INIT_RATIO]*/
   	0x79,        /* **DDR3_CONFIG_17 [DATA3_PHY_GATELVL_INIT_RATIO]*/
   	0,           /* **DDR3_CONFIG_18 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_19 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_20 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_21 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_22 [DATA8_PHY_GATELVL_INIT_RATIO]*/
   	0x08d13434,  /* **DDR3_CONFIG_23 [WR_DATA_SLAVE_RATIO, WR_DQS_SLAVE_RATIO, RD_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_24 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_25 [DATA0_FIFO_WE_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_26 [DATA0_FIFO_WE_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_27 [DATA0_FIFO_WE_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_28 [DATA0_FIFO_WE_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_29 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_30 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_31 [NA for C665x]*/
   	
   	0,           /* DDR3_CONFIG_32 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_33 [DATA_ECC_FIFO_WE_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_34 [DATA0_WR_DATA_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_35 [DATA0_WR_DATA_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_36 [DATA0_WR_DATA_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_37 [DATA0_WR_DATA_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_38 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_39 [NA for C665x]*/
       0,           /* DDR3_CONFIG_40 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_41 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_42 [DATA_ECC_WR_DATA_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_43 [DATA0_WR_DQS_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_44 [DATA1_WR_DQS_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_45 [DATA2_WR_DQS_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_46 [DATA3_WR_DQS_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_47 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_48 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_49 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_50 [NA for C665x]*/
   	0,           /* DDR3_CONFIG_51 [DATA_ECC_WR_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_52 [DATA0_RD_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_53 [DATA1_RD_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_54 [DATA2_RD_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_55 [DATA3_RD_DQS_SLAVE_RATIO]*/
   	0,           /* **DDR3_CONFIG_56 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_57 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_58 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_59 [NA for C665x]*/
   	0,           /* **DDR3_CONFIG_60 [DATA_ECC_RD_DQS_SLAVE_RATIO]*/
   	0,           /* DDR3_CONFIG_61 [NA]*/
   	0,           /* DDR3_CONFIG_62 [NA]*/
   	0            /* DDR3_CONFIG_63 [NA]*/
   };
   #else
   	const BOOT_EMIF4_TBL_T  emif4Cfg =  {
   
       BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
       BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
       BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
       BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
   	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
   	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,
   
       BOOT_EMIF_ENABLE_SLSW_config0 | \
   	BOOT_EMIF_ENABLE_SLSW_config6 | \
   	BOOT_EMIF_ENABLE_SLSW_config7 | \
   	BOOT_EMIF_ENABLE_SLSW_config8 | \
   	BOOT_EMIF_ENABLE_SLSW_config9 | \
   	BOOT_EMIF_ENABLE_SLSW_config10 | \
   	BOOT_EMIF_ENABLE_SLSW_config18 | \
   	BOOT_EMIF_ENABLE_SLSW_config19 | \
   	BOOT_EMIF_ENABLE_SLSW_config20 | \
   	BOOT_EMIF_ENABLE_SLSW_config22 | \
   	BOOT_EMIF_ENABLE_SLSW_config12 | \
   	BOOT_EMIF_ENABLE_SLSW_config23 | \
   	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
       0,      /* Config select lsw  */
       
       3,      /* pllPrediv  */
       40,     /* pllMult    */
       2,      /* pllPostDiv */
   
       0x62477AB2,  /* sdRamConfig */
       0,           /* sdRamConfig2, dont care*/
       0x0000144F,  /* sdRamRefreshCtl  */
       0x1333780C,  /* sdRamTiming1 */
       0x30717FE3,  /* sdRamTiming2 */
       0x559F86AF,  /* sdRamTiming3 */
   
       0,           /* lpDdrNvmTiming, dont care */
       0,           /* powerManageCtl, dont care */
       0,           /* iODFTTestLogic, dont care */
       0,           /* performCountCfg, dont care */
       0,           /* performCountMstRegSel, dont care */
       0,           /* readIdleCtl, dont care */
       0,           /* sysVbusmIntEnSet, dont care */
       0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
       0,           /* tempAlterCfg, dont care */
   
       0x0010010F,  /* ddrPhyCtl1 */
   
       0,           /* ddrPhyCtl2, dont care */
       0,           /* priClassSvceMap, dont care */
       0,           /* mstId2ClsSvce1Map, dont care */
       0,           /* mstId2ClsSvce2Map, dont care */
       0,           /* eccCtl, dont care */
       0,           /* eccRange1, dont care */
       0,           /* eccRange2, dont care */
       0,           /* rdWrtExcThresh, dont care */
   
       0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
       0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
       0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
       0, 0, 0, 0, 0, 0, 0, 0,
       
       0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0
   };
   #endif
   
   
   
   void main(void)
   {
       volatile uint32_t *BOOT_COMPLETE        = (volatile uint32_t *)0x0262013C;
       volatile uint32_t *PIN_CONTROL_0        = (volatile uint32_t *)0x02620580;
       volatile uint32_t *GPIO_C6657_DIR       = (volatile uint32_t *)(0x02320000 + 0x10);
       volatile uint32_t *GPIO_C6657_OUT_DATA  = (volatile uint32_t *)(0x02320000 + 0x14);
       uint32_t loop_cnt = 0;
   
       *BOOT_COMPLETE  = 0x00000003;// Set BootComplete 0 and 1
       *PIN_CONTROL_0  = 0x00200000;
       *GPIO_C6657_DIR = 0xFFDFFFFF;// GPIO21 Output
       for (loop_cnt = 0; loop_cnt < 0x0FFFFFFF; loop_cnt++) {
           uint32_t x;
           for (x=0; x<0x1fffffe;x++) {
               *GPIO_C6657_OUT_DATA = 0x00200000;// GPIO21 High
           }
   
           for (x=0; x<0x1fffffe;x++) {
               *GPIO_C6657_OUT_DATA = 0x0; // GPIO21 Low
           }
       }
   //    asm("	IDLE");
   }
       
   

   
   
   After following the building instructions in the application note the app.dat file is 
   app.dat
   

   This file has been successfully loaded into the EVM and booted.  This file basically just toggles the GPIO21/UARTTXD pin at a rate that is monitorable by a DMM.  This is the file I am loading onto our custom hardware.

2. What is the length value set during "load memory option" in the length in memory words section? 
    

Earlier in this conversation I went through the steps I used to create this example and that I had loaded the example on both the EVM and my custom hardware including what the DEVSTAT register value. 

Please see my discussion around this post.

BradS said:

Run the internal RAM example on the Custom Hardware

I hope this answers your questions.

Brad

BradS said:

Changed the boot mode pins to SPI Boot. (Validated by connecting with the XDS200 and seeing what the DEVSTAT register is showing C66xx_0: GEL Output: DEVSTAT 0x0001840D Bootmode = 0x00000006.

--

The 40D matches in the DEVSTAT.

Let us focus on the other bits of DEVSTAT - 0x00018 -

--

14 to 15th bit --- 10b = PCIe in Root complex mode

16th bit --- 1 = PCIe module enabled

--

The values 00018 should not be suspected to be an impact  SPI-boot mode.

But however, is it possible to disable the PCIE module? temporarily ? and check whether it boots?

--

Next thing, is, let me give a sample few lines of code to be inserted inside the spi-direct boot code.....

Regards

Shankari G

I have modified our custom board to have the PCIe configuration lines all tied low.  I have attempted to boot the processor from the SPI but still no success.  I then connected the debugger and verified DEVSTAT register (DEVSTAT  = 0x0000040D  Bootmode = 0x00000006).

Then I proceeded to verify that the application if it loaded properly would work.  I did this by: after connecting with the debugger, I loaded the spiboot.out file and ran the program.  On my hardware the BootComplete line is activated and the GPIO21/UARTTXD toggles. (as expected).

Anything else you would like me to try?

Brad,

Let us do this one simple/similar test on your C6657 EVM as-well-as on your custom hardware.

========================================================

Case (1) : On C6657 EVM using " No boot mode" -  CCS + XDS + GEL ( Have a glance at the video below)

========================================================

Boot mode: "No boot"

1. Download the spiboot.c given below. ( Not to modify any code )

/* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "tiboot.h"
#include "platform.h"

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

#define GPIO_BASE (0x2320000)
#define GPIO_DIR_OFFSET (0x10)
#define GPIO_SETDATA_OFFSET (0x18)
#define GPIO_CLEARDATA_OFFSET (0x1C)
	
void main(void)
{

    volatile uint32_t *reg_val;

     reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
     // configure as output pin -- write 0 to the Direction register
     *reg_val &= ~ (1 << 8);


     reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
     // Write value 1 in the set data register, so that Out data register will be 1
     *reg_val |= (1 << 8);
    while (1)
    {
        asm("	IDLE");
    }

}
	

2. Download the spiboot.cmd given below. ( Not to modify any code )

spiboot.obj

-c
-a
-stack 0x400

MEMORY
{
    DDR_CFG   :  origin = 0x8ffd20, length = 0x180
	L2MAGIC   :  origin = 0x8ffffc, length = 0x4

	DDR       :  origin = 0x80000000, length = 0x2000
}


SECTIONS
{
    .emif4Cfg > DDR_CFG

	.stack > DDR
	.msmc  > DDR
	.data  > DDR
	.far   > DDR
	.text  > DDR
	.const > DDR
	.cinit > DDR
	.lmagic > L2MAGIC
	

}

3. Build the spiboot.c using "gmake" and get spiboot.out . 

3.1 --> Note the size of the spiboot.out file as 60 KB  ( later, this value may help in comparing the size of the actual application binary, for your custom hardware, while loading and booting from SPI-NOR )

4. Connect the C6657 EVM with CCS +XDS and launch the target configuration file. Do "connect target" and let it run the gel file and produce outputs on the console. ( Share the gel-file-output messages to me)

5. Load the core 0 with spiboot.out and run.

Observe the Outputs: 

6. Go to register view option  in ccs and hit "DDR3". Export the register values into a doc. ( Share it to me ) .

Please note the that DDR3 is configured...[ please Compare the DDR3 values when you run the gel file, before loading the spiboot.out and after loading-and-running the spiboot.out) 

7. Go to memory browser window and feed the GPIO register address as "0x2320000 " . (Take a screenshot like below and share it to me ).

Please note that the value will get changed as "00000100" in GPIO_bank_registers_out_data.

video: 

========================================================================================================

Case (2) : On C6657 EVM using "SPI-boot mode" after flashing into NOR memory using NOR-writer. ( Before, starting the test, Have a glance on the video below )

========================================================================================================

1. The same, spiboot.c ( Not to modify any code )

2. The same, spiboot.cmd ( Not to modify any code )

3. Build the spiboot.c using "gmake" and get spiboot.out . 

4. Convert the .out into app.dat and note the size of the  app.dat as "12KB "

5. open the app.dat in ccs and modify the offset value 51 as 00  - as given in the SPIboot_with_DDR_UserGuide.docx

5. Have the board in "No-boot mode" . Connect to ccs, launch cxml, load the Nor-writer.out.  Using memory load option, locate the app.dat, select the binary as "TI Data". Click "next" option, select the address as "0x80000000 " and the length as "0x4000" or 0xC000"

6. Note the console messages like below.

7. Now, change the boot mode as SW3 {pin 0 - pin8) = 10110000 (0-ON, 1-OFF) SW5(pin0 - pin8) = 00100000.

8. Power on the board

9. Connect to XDS. Launch cxml. Do connect target. It will display the bootmode value as "6" in the console.

9. Go to register view - compare the values of DDR3 with the values in teh spiboot.c

7. Go to memory browser window and feed the GPIO register address as "0x2320000 " . (Take a screenshot like below and share it to me ).

Please note that the value will get changed as "00000100" in GPIO_bank_registers_out_data.

THIS SCREENSHOT VALUES SHOULD MATCH WITH THE ABOVE , CASE(1), STEP 7 SCREENSHOT.

This will prove that the SPIBOOT works and executes the code inside the main()of spiboot.c

---

===========================================

Case 3: On your custom hardware using "No boot" mode  

===========================================

1. Not to modify the spiboot.c and spiboot.cmd

2. Repeat the same test by following the steps given in case ( 1 ) with your custom hardware

~~~~~~~~~~~~~~

List of things to do: - Compare case ( 1 ) vs case ( 3)

~~~~~~~~~~~~~~~

1. compare the gel file of C6657 evm and your custom hardware's gel. Analyze the differences.

2. Compare the ddr3 register values in the ccs register window - C6657 EVM vs the custom hardware - Analyze the differences.

3. compare the screenshot of GPIO register values - C6657 EVM vs the custom hardware - Analyze the differences. 

If the output is same, then the ddr3, gpio functions properly in the custom hardware. 

Let me know your observations in case (3) and also

     - Share me the GPIO output screenshot in ccs

      - Export the ddr3 register values from ccs  and share .

     - share the Gel source of your custom hardware

     - Share the gel output

============================================

Case 4: On your custom hardware using "SPI-boot mode" after flashing into NOR memory using NOR-writer. 

===========================================

1. Not to modify the spiboot.c and spiboot.cmd

2. Repeat the same test by following the steps given in case ( 2 ) with your custom hardware

~~~~~~~~~~~~~~

List of things to do:

~~~~~~~~~~~~~~~

1. Compare the gel console output messages - with my screenshot posted in step 9 - case ( 2) 

2. Compare the ddr3 register values in the ccs register window - with your case (3) ddr3 values - Analyze the differences.

3. compare the ddr3 register values in the ccs register window - with the ddr3 emif4Cfg values in the spiboot.c

4. compare the screenshot of GPIO register values - with your case (3) - screenshot ( THIS SCREENSHOT should give the same ouput for all your case (1, 2, 3 and 4)

Let me know your observations in case (4)

     - Share me the GPIO output screenshot in ccs

      - Export the ddr3 register values from ccs  and share .

     - Share the gel output with boot mode value

===========================================

Regards

Shankari G

Answers to your questions.

NOTE: In the following response I attempted to export the DDR3 registers.  However when attempting to do so, errors were reported in the console window, "Unable to save register DDR3_", and no data was saved into the .txt file.

Case 1: EVM using "NoBoot"

1. Copied the spiboot.c and spiboot.cmd to my build directory.
2. Ran the make file and a ~60kB sipboot.out file was created.
3. Connected to the C6657 EVM using the emvc6657l gel file. Gel results:
   
4. DDR3 Registers at this point
   
5. Load the spidata.out file the registers now show
   
6. After running the application with the following results.
     

Case 2: EVM using "SPI-Boot"

1. Build the same program for SPI load following the information in the SPIboot_with_DDR_UserGuide.docx
   1. Changed the "0x51 to 0x00" change to the app.dat file
   2. The app.dat file is 12kB in size.
   3. Loaded the norwriter application.  Loaded memory with app.dat setting of: addr 0x80000000 size of 0xC000.
      1. NOTE: on the console a warning was produced "C66xx_0: Unexpected end of file: C:/ti/pdk_c665x_2_0_16/packages/ti/boot/writer/nor/evmc6657l/bin/app.dat. Only 3780 bytes are loaded from the file into the memory and the remaining bytes are set to zero."
   4. Ran the norwriter
      
2. Changed the EVM boot mode to SW3 {pin 0 - pin8) = 10110000 (0-ON, 1-OFF) SW5(pin0 - pin8) = 00100000.
3. Powered the board and connected the debugger.  The DDR3 values are:
   

Case 3: Custom Hardware "No Boot"

1. My custom Gel file will also operate on the EVM.  Basically the only changes are: 
   
   1. Modified the DDR memory test to be configurable for the test length and added a GEL_TextOut to four times during each part of the DDR memory test.
   2. Modified to print the DEVSTAT and bootmode values each time the debugger connects.
   3. Added GEL_TextOut prints to indicate the start as finish of each function in the gel file.
   4. Changed the memory initialization call from ddr3_setup_auto_lvl_1333(0); to ddr3_setup_auto_lvl_1333();  since no variables are passed to the ddr3_setup_auto_lvl_1333 function.
   5. Modified the DATAx_WRLVL_INIT_RATIO values to those obtained form the calculation spreadsheets for my hardware.
   6. Modified the DDR_SDTIM2, DDR_SDTIM3 and DDR_SDCFG to those from the spreadsheet calculations.
   7. NOTE: My custom GEL file, saratoga_1333.gel, also works with the EVM!!!!
2. Connected to the target with the debugger
   1. Loaded my custom gel file (referenced above saratoga_1333.gel)
   2. Upon connection the gel file runs, the results of the gel file are shown on the left the DDR3 memory is shown in the middle and the GPIO pin status is on the right.
      
   3. The results are consistent with Case 1 with the EVM

Case 4: Custom Hardware "SPI-Boot"

1. The same norwriter application was used.  The same spiboot application was loaded into 0x80000000 with a size of 0xC000.
2. The norwriter was executed with the following results. 
   
   
3. The bootmode pins were changed to SPI boot.
4. Applied power to the board.
5. Connected the debugger and monitored the console DDR3 registers and the GPIO configuration.
   

Test Results:

1.  Analysis
   1. The gel outputs match that of the EVM case. (i.e. it reports that the bootmode configuration is SPI boot 
   2. The DDR3 memory configuration does NOT match that of the custom hardware NoBoot test.
   3. The DDR3 values do NOT match that of the emif4cfg values.
   4. The GPIO registers do NOT match that of the other three cases.
2. As noted at the top of the post, when attempting to export the DDR3 registers the console reported errors.  So that data is not included (just screen shots.

It appears that I have made no progress towards my goal of booting the processor directly for the SPI NOR memory.

Question regarding additional research on this site.

I have been searching your site for additional information and came upon this post https://e2e.ti.com/support/processors-group/processors/f/processors-forum/832349/tms320c6657-bootloader-for-c6657  It appears to state that TI does not recommend using the ROM bootloader to configure the DDR3 and directly load the program into DDR3 memory.  Is this true? 

Thanks,

Brad

Brad,

BradS said:

I have been searching your site for additional information and came upon this post https://e2e.ti.com/support/processors-group/processors/f/processors-forum/832349/tms320c6657-bootloader-for-c6657  It appears to state that TI does not recommend using the ROM bootloader to configure the DDR3 and directly load the program into DDR3 memory.  Is this true? 

Yes, In RBL, the DDR3 configuration is limited.

That's why in spiboot.c, we are completing the configuration of DDR3. The Direct boot example is not RBL.

The RBL will invoke the direct boot SPI-example with DDR configurations. Our approach is right.

Case 2:

===== 

The console of NOR writer message seems to be re-checked?  When we feed the length as 0x4000, it says 3780? 

It should somehow display that the 3780 bytes of data ( Check in my video - case 2) 

Case 4:

======

The console of NOR writer message seems to be re-checked?   When we feed the length as 0x4000, it says 3780? 

It should somehow display that the 3780 bytes of data ( Check in my video - case 2) 

--

Let me know, what differences you observed,

==================================

1. In the gel source of your EVM vs the custome hardware. List it down, one by one;

2.  In the gel output of your EVM vs the custom hardware. List it down, one by one;

3. The ddr3 register values of your EVM Vs the custom hardware. List it down, one by one;

Let us understand the significance of each difference.

Regards

Shankari G

Shankari G said:

Case 2:

===== 

The console of NOR writer message seems to be re-checked?  When we feed the length as 0x4000, it says 3780? 

It should somehow display that the 3780 bytes of data ( Check in my video - case 2) 

Case 4:

======

The console of NOR writer message seems to be re-checked?   When we feed the length as 0x4000, it says 3780? 

It should somehow display that the 3780 bytes of data ( Check in my video - case 2) 

I am using NOR Writer Utility Version 01.00.00.04 from the C:\ti\pdk_c665x_2_0_16\packages\ti\boot\writer\nor\evmc6657l\bin directory and you are using NOR Writer Utility Version 01.00.00.03 from the C:\ti\2781.C6657_directROM_Boot_example\C6657\SPIboot_ddr\bin\flashwriter directory.  I have tried both versions of the NOR Writer and they both produce the exact same results.

Shankari G said:

1. In the gel source of your EVM vs the custome hardware. List it down, one by one;

I have used the same gel file for both the EVM and the Custom Hardware, saratoga_1333.gel (file is included in the chat above.), to establish a connection and properly configure the DDR3 memory.  So therefore there is no difference between the two pieces of hardware.

Shankari G said:

2.  In the gel output of your EVM vs the custom hardware. List it down, one by one;

The only difference when running the same gel file is the boot pins. The custom hardware's DEVSTAT  = 0x00000401 and the EVM's  DEVSTAT  = 0x00000001.  This difference exists since we use pull up and downs to configure the boot pins and the EVM uses the FPGA's programable outputs.

Shankari G said:

3. The ddr3 register values of your EVM Vs the custom hardware. List it down, one by one;

After connecting to the custom hardware and EVM using the saratoga_1333.gel file.  I dumped the DDR3 registers and compared.  The only difference is in the perf_cnt_tim with (custom board value 0xA08CEAC7 and the EVM's 0x04E77E50.

 According to SPRUGV8E this is just a counter that reports the number of DDR/2 clock cycles since reset.

So... essential there is no difference between the custom hardware and the EVM.

Do you have any additional suggestion for gathering additional information on this issue?

Lets take a step back here and analyze all the tests we have performed...

A little while back in the conversation I wen through a set of tests that 1) Created an application that would load and run from the DDR3 memory on the EVM.  2) Modified this application to just use internal memory (thereby eliminating the DDR3 configuration issue).  This application worked on the EVM but did not work on the custom hardware.  So in my mind the current issue is with the SPI boot communications and  not with the DDR3 memory.  Do you agree?  My question regards to this is: What is the SPI clock rate when the processor boots from SPI? 

Brad,

Please hold on before we move into the SPI-clock. ( That is also actually an important factor, we will look at in a while.... )

--

Firstly,

The diff value of DEVSTAT register is important.

In no-boot mode the value of DEVSTAT is 0x00000401 for custom hardware; Whereas in the EVM it is 0x00000001.

When this value is decoded with Devstat[13-1] == BOOTMODE[12:0] - page no: 205 https://www.ti.com/lit/ds/symlink/tms320c6657.pdf.

If the 9th bit of Boot mode is 1, it denotes the "Addr Width" for SPI-boot mode....

    ---> SPI address width configuration

          • 0 = 16-bit address values are used

          • 1 = 24-bit address values are used

Since it is a custom hardware, analyze, why the DEVSTAT doesnot give 0x00000001 when you use gel file + CCS???? 

As it is in NO-boot mode, the 9th bit value is a reserved... However, after flashing, it matters, when the boot pins are changed for SPI-boot mode, right??

In case 4, what is the value of your DEVSTAT ? -- Recheck -- in the memory browser with address - "0x02620020"

My DEVSTAT value is - 0000040D

----

Secondly,

In your case (4) test , check the program counter value and map it with your spiboot.map

Follow the video below and do.

1. Post your pc counter value 

2. Post your spiboot.map.

3. Please post video on your case 4 with PC - program counter value and the GPIO address access in the memory browser....

If we could locate the PC address within th map, then most likely the SPI_Boot-direct example runs and executed by the RBL.

----

In your snapshot of cae4, 

Thirdly, compare the SPI-NOR flash part used in the EVM vs the custom hardware.

Most importantly, check the number of available modes.

For example, in the EVM, N25Q032A is used and the modes supported are two.

https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf

Table 7: SPI Modes Note 1 applies to the entire table

SPI Modes                         Clock Polarity  

CPOL = 0, CPHA = 0     C remains at 0 for (CPOL = 0, CPHA = 0)

CPOL = 1, CPHA = 1     C remains at 1 for (CPOL = 1, CPHA = 1)

------

Regards

Shankari G

Brad,

Please hold on before we move into the SPI-clock. ( That is also actually an important factor, we will look at in a while.... )

--

Firstly,

The diff value of DEVSTAT register is important.

In no-boot mode the value of DEVSTAT is 0x00000401 for custom hardware; Whereas in the EVM it is 0x00000001.

When this value is decoded with Devstat[13-1] == BOOTMODE[12:0] - page no: 205 https://www.ti.com/lit/ds/symlink/tms320c6657.pdf.

If the 9th bit of Boot mode is 1, it denotes the "Addr Width" for SPI-boot mode....

    ---> SPI address width configuration

          • 0 = 16-bit address values are used

          • 1 = 24-bit address values are used

Since it is a custom hardware, analyze, why the DEVSTAT doesnot give 0x00000001 when you use gel file + CCS???? 

As it is in NO-boot mode, the 9th bit value is a reserved... However, after flashing, it matters, when the boot pins are changed for SPI-boot mode, right??

In case 4, what is the value of your DEVSTAT ? -- Recheck -- in the memory browser with address - "0x02620020"

My DEVSTAT value is - 0000040D

----

Secondly,

Download the spiboot.c- given-below and repeat case ( 4) , to confirm whether the RBL invokes the Direct spi-boot example.

In your case (4) test , check the program counter value and map it with your spiboot.map

My spiboot.c - 

/* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "tiboot.h"
#include "platform.h"

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

#define GPIO_BASE (0x2320000)
#define GPIO_DIR_OFFSET (0x10)
#define GPIO_SETDATA_OFFSET (0x18)
#define GPIO_CLEARDATA_OFFSET (0x1C)

void testfunc();

void testfunc()
{

    while (1)
    {
        asm("   IDLE");

    }
}

void main(void)
{

    volatile uint32_t *reg_val;

     reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
     // configure as output pin -- write 0 to the Direction register
     *reg_val &= ~ (1 << 8);


     reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
     // Write value 1 in the set data register, so that Out data register will be 1
     *reg_val |= (1 << 8);
    testfunc();


}
	

Follow the video below and do.

1. Post your pc counter value 

2. Post your spiboot.map.

3. Please post video on your case 4 with PC - program counter value and the GPIO address access in the memory browser....

If we could locate the PC address within th map, then most likely the SPI_Boot-direct example runs and executed by the RBL.

----

In your snapshot of case4, 

Thirdly, compare the SPI-NOR flash part used in the EVM vs the custom hardware.

Most importantly, check the number of available modes.

For example, in the EVM, N25Q032A is used and the modes supported are two.

https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf

Table 7: SPI Modes Note 1 applies to the entire table

SPI Modes                         Clock Polarity  

CPOL = 0, CPHA = 0     C remains at 0 for (CPOL = 0, CPHA = 0)

CPOL = 1, CPHA = 1     C remains at 1 for (CPOL = 1, CPHA = 1)

------

Regards

Shankari G

Brad,

Please hold on before we move into the SPI-clock. ( That is also actually an important factor, we will look at in a while.... )

--

Firstly,

The diff value of DEVSTAT register is important.

In no-boot mode the value of DEVSTAT is 0x00000401 for custom hardware; Whereas in the EVM it is 0x00000001.

When this value is decoded with Devstat[13-1] == BOOTMODE[12:0] - page no: 205 https://www.ti.com/lit/ds/symlink/tms320c6657.pdf.

If the 9th bit of Boot mode is 1, it denotes the "Addr Width" for SPI-boot mode....

    ---> SPI address width configuration

          • 0 = 16-bit address values are used

          • 1 = 24-bit address values are used

Since it is a custom hardware, analyze, why the DEVSTAT doesnot give 0x00000001 when you use gel file + CCS???? 

As it is in NO-boot mode, the 9th bit value is a reserved... However, after flashing, it matters, when the boot pins are changed for SPI-boot mode, right??

In case 4, what is the value of your DEVSTAT ? -- Recheck -- in the memory browser with address - "0x02620020"

My DEVSTAT value is - 0000040D

----

Secondly,

Download the spiboot.c- given-below and repeat case ( 4) , to confirm whether the RBL invokes the Direct spi-boot example.

In your case (4) test , check the program counter value and map it with your spiboot.map

My spiboot.c - 

/* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "tiboot.h"
#include "platform.h"

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

#define GPIO_BASE (0x2320000)
#define GPIO_DIR_OFFSET (0x10)
#define GPIO_SETDATA_OFFSET (0x18)
#define GPIO_CLEARDATA_OFFSET (0x1C)

void testfunc();

void testfunc()
{

    while (1)
    {
        asm("   IDLE");

    }
}

void main(void)
{

    volatile uint32_t *reg_val;

     reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
     // configure as output pin -- write 0 to the Direction register
     *reg_val &= ~ (1 << 8);


     reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
     // Write value 1 in the set data register, so that Out data register will be 1
     *reg_val |= (1 << 8);
    testfunc();


}
	

Follow the video below and do.

1. Post your pc counter value 

2. Post your spiboot.map.

3. Please post video on your case 4 with PC - program counter value and the GPIO address access in the memory browser....

If we could locate the PC address within th map, then most likely the SPI_Boot-direct example runs and executed by the RBL.

----

In your snapshot of case4, 

Thirdly, compare the SPI-NOR flash part used in the EVM vs the custom hardware.

Most importantly, check the number of available modes.

For example, in the EVM, N25Q032A is used and the modes supported are two.

https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf

Table 7: SPI Modes Note 1 applies to the entire table

SPI Modes                         Clock Polarity  

CPOL = 0, CPHA = 0     C remains at 0 for (CPOL = 0, CPHA = 0)

CPOL = 1, CPHA = 1     C remains at 1 for (CPOL = 1, CPHA = 1)

------

Regards

Shankari G

Shankari G said:

As it is in NO-boot mode, the 9th bit value is a reserved... However, after flashing, it matters, when the boot pins are changed for SPI-boot mode, right??

In case 4, what is the value of your DEVSTAT ? -- Recheck -- in the memory browser with address - "0x02620020"

My DEVSTAT value is - 0000040D

As shown earlier in the conversation, when the boot configuration is set to SPI boot the value of the DEVSTAT register is the same for both the EVM and the custom hardware.  After your request, we modified all of the lines to match that of the EVM's SPI boot configuration.

BradS said:

 I have attempted to boot the processor from the SPI but still no success.  I then connected the debugger and verified DEVSTAT register (DEVSTAT  = 0x0000040D  Bootmode = 0x00000006).

As stated earlier our custom hardware uses pullup and pulldown resistors to configure most of the boot configuration lines.  We determined that during development we would need to configure the hardware for no boot we included switches for bootmode[2:0].  Let me make this completely clear. bootmode[2:0] are easily changed from high to low, but bootmode[12:3] require board modifications(ie. add/remove resistors) to change from high to low.

Testing with the revised spiboot.c...

Due to the fact that we work on ITAR related material, I am working with our Export Control department to get approval and limitation to allow for posting screen capture video from our workstations.  As of right now I do not have that approval.  I will start adding that type of information when allowed.

• Compiled the new spiboot.c. Loaded onto custom hardware using v1.0.0.3 of NORNOR writer utility.
  
• Changed the bootmode lines to SPI boot and restarted the unit.  Then connected the debugger to the unit and got the following results
   (Stopped on some random address.)
• Used the same technique to load the EVM and got the following
  (ie. the expected results)

Question:

With all of this testing I am starting to believe that the NOR SPI-writer program is not writing the proper data into the flash memory on my custom hardware.  Is there a configuration option of the writer that would transmit the data that is to be written and read from the SPI memory out the UART port?  This would allow me validate that the expected data is without a doubt being properly written and verified/read from the SPI memory?

Description of the SPI interface of our custom hardware.

We use the N25Q064A11ESEA0F SPI memory (should be the larger version of the memory on the EVM).  Between the SPI memory is connected to a SN74AVC4T774 buffer, to buffer the signals(6nS of delay), and then a 10Ohm resistor inline with each of the signals before they are connected to the C6657.  So whatever works on the EVM should work on the custom hardware.  I have tapped these lines with a scope and validated that they are changing states in a somewhat expected manor. (basically I do not believe that there is an issue with the SPI hardware, but who knows.) The only other difference between the two boards is that we have tied the W#/Vpp/DQ2 high where on the EVM this line is driven high by the FPGA.

Brad,

As I already requested, in my previuos post, 

For your case (4) on your custom board,  

1. Post your pc counter value - ( Let it be a snapshot, if no video....) 

2. Post your spiboot.map. - ( Load it in text format)

---

1. Is your second snapshot is on your custom hardware?  with the random PC address, which doesnot mapp with the spiboot.map?, Please post your spiboot.map, without that, I could not verify.....

2. Is your third snapshot is on the C6657 EVM and not your custom hardware, right? That PC address is pointing to the test func() in the spiboot.map as expected !!

--

This is.... what is... is directing me to think...... 

As the SPI-NOR writer works properly, it even says, "reading and veryfing successfully" which means, it writes properly on the NOR memory.

It even reads back and verify the data....

----> And importantly, the CCS gel file +  NOR-writer program in the "custom hardware" knows to communicate correctly with the SPI ....

-----> But the same configuration is missing  in the RBL + Direct boot-SPI program in the custom hardware ?? ( I guess, this cannot be the case because, with the same RBL + Direct-spi works in the EVM, right? )

-----> But the same configuration is present in the RBL + Direct boot-SPI program in the C6657EVM !! ?? 

And hence, Boot mode pins and its configuration on your custom hardware may need more focus....

Down the line, it could be a hardware problem, as we validated all the possiblities in software.

-----

BradS said:

With all of this testing I am starting to believe that the NOR SPI-writer program is not writing the proper data into the flash memory on my custom hardware.  Is there a configuration option of the writer that would transmit the data that is to be written and read from the SPI memory out the UART port?  This would allow me validate that the expected data is without a doubt being properly written and verified/read from the SPI memory?

Not sure, it is worth spending time on the writer, adding the memory-out on "UART". Because, I have no doubt on the Writer.... as it verifies the data.... 

 Regards

Shankari G

Brad,

In your second snapshot, your PC counter with value 20B11B52, denotes.... that it stays at the RBL https://www.ti.com/lit/ds/symlink/tms320c6657.pdf

Page no:166.

Hence, the DDR3 configuration seems to be not-done properly for your custom board.

With reference to your gel file ( saratoga_1333.gel)  of your custom hardware, the values of const BOOT_EMIF4_TBL_T  emif4Cfg has to be matched and updated in spiboot.c.

When I see the difference between the C6657evm.gel and your saratoga_1333.gel, there are lot of DDR3 timing parameters and Automatic Leveling parameter changes for your custom board.

--

And also, 

1. Flash and run the same program in internal memory-L2_DATA by removing the DDR3 completely both in spiboot.c and spiboot.cmd - refer below

2. Check the program counter and post it -- Important

And now, your custom board should boot without DDR3.

===========spiboot.c=========

Remove the entire structure. 

#pragma DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T emif4Cfg 

==============Spiboot.cmd============
spiboot.obj

-c
-a
-stack 0x400

MEMORY
{
L2MAGIC : origin = 0x8ffffc, length = 0x4
L2_DATA : origin = 0x800000, length = 0xff000
}

SECTIONS
{
.stack > L2_DATA
.msmc > L2_DATA
.data > L2_DATA
.far > L2_DATA
.text > L2_DATA
.const > L2_DATA
.cinit > L2_DATA
.lmagic > L2MAGIC

}

Regards

Shankari G

From your first response:

Shankari G said:

1. Is your second snapshot is on your custom hardware?  with the random PC address, which doesnot mapp with the spiboot.map?, Please post your spiboot.map, without that, I could not verify.....

2. Is your third snapshot is on the C6657 EVM and not your custom hardware, right? That PC address is pointing to the test func() in the spiboot.map as expected !!

You are correct in your assumptions.  The first screen shot was included to show that the NOR writer program completed as expected on the custom hardware.  The second screen shot was included to show the results after reconfiguring the custom hardware for SPI boot.  The third screen shot was included to show that the code was properly created and runs as expected on the EVM hardware.

Shankari G said:

This is.... what is... is directing me to think...... 

As the SPI-NOR writer works properly, it even says, "reading and veryfing successfully" which means, it writes properly on the NOR memory.

It even reads back and verify the data....

----> And importantly, the CCS gel file +  NOR-writer program in the "custom hardware" knows to communicate correctly with the SPI ....

-----> But the same configuration is missing  in the RBL + Direct boot-SPI program in the custom hardware ?? ( I guess, this cannot be the case because, with the same RBL + Direct-spi works in the EVM, right? )

-----> But the same configuration is present in the RBL + Direct boot-SPI program in the C6657EVM !! ?? 

And hence, Boot mode pins and its configuration on your custom hardware may need more focus....

Down the line, it could be a hardware problem, as we validated all the possiblities in software.

I agree with these statements.

With the information that the processor is still executing in the RBL, this must mean that the RBL is not getting the proper information to boot.  Right now I believe that at least three things could be causing this issue with the custom hardware.
A) the NORwriter tool did not properly write the data to the memory, or
B) the SPI memory has some sort of issue right after boot, or
C) the RBL is not configured properly, or
D) there is some other sort of board issue.

I am questioning the NORwriter tool because when running the app it take significantly longer for the NORwriter to complete it's write and verification when running on the custom hardware. (i.e. EVM completes quickly <5sec and the custom hardware completes in 20-30sec)

I would like to work methodically through these options to confirm or eliminate them as a source of my issue.  I would like to validate that the flash memories can be read.   I would like to validate that the information in the memories is the same between the EVM and the custom hardware.

Second reply...

Shankari G said:

With reference to your gel file ( saratoga_1333.gel)  of your custom hardware, the values of const BOOT_EMIF4_TBL_T  emif4Cfg has to be matched and updated in spiboot.c.

When I see the difference between the C6657evm.gel and your saratoga_1333.gel, there are lot of DDR3 timing parameters and Automatic Leveling parameter changes for your custom board.

I agree, these values need to change for the custom hardware to properly access the DDR memory. (This is why I was trying to boot to internal memory, since it was appearing that the issue was with getting the proper information into the part to boot.)

1. Test without the DDR3 configuration.
   This test is essentially the test I documented 12 days ago, where I removed the DDR configuration, compiled and loaded the code and it did not work.  In my test code the first line of the code would cause the BOOTCOMPLETE line to drive HIGH (which it did not).
   1. Removed the references to the emif4Cfg, and recompiled the code.  Loaded onto both platforms with NOR writer ver 1.00.00.03.  Both platforms reported a successful load (however the custom hardware load took longer to complete).  Rebooted both platforms in SPI boot mode.  After reconnecting the debugger the EVM was stopped at the expected memory location.  The custom hardware was stopped somewhere within the RBL.
      

      ******************************************************************************
                     TMS320C6x Linker PC v7.4.24                     
      ******************************************************************************
      >> Linked Wed Oct 19 08:17:55 2022
      
      OUTPUT FILE NAME:   <spiboot.out>
      ENTRY POINT SYMBOL: "_c_int00"  address: 00000000
      
      
      MEMORY CONFIGURATION
      
               name            origin    length      used     unused   attr    fill
      ----------------------  --------  ---------  --------  --------  ----  --------
        L2MAGIC               008ffffc   00000004  00000000  00000004  RWIX
        DDR                   80000000   00002000  00000000  00002000  RWIX
      
      
      SEGMENT ALLOCATION MAP
      
      run origin  load origin   length   init length attrs members
      ----------  ----------- ---------- ----------- ----- -------
      00000000    00000000    0000000c   0000000c    rw-
        00000000    00000000    0000000c   0000000c    rw- .fardata
      00000000    00000000    0000001d   0000001d    r--
        00000000    00000000    0000001d   0000001d    r-- .cinit
      00000000    00000000    00000400   00000000    rw-
        00000000    00000000    00000400   00000000    rw- .stack
      00000000    00000000    00000920   00000920    r-x
        00000000    00000000    00000920   00000920    r-x .text
      
      
      SECTION ALLOCATION MAP
      
       output                                  attributes/
      section   page    origin      length       input sections
      --------  ----  ----------  ----------   ----------------
      .fardata   0    00000000    0000000c     FAILED TO ALLOCATE
      .cinit     0    00000000    0000001d     FAILED TO ALLOCATE
      .stack     0    00000000    00000400     FAILED TO ALLOCATE
      .text      0    00000000    00000920     FAILED TO ALLOCATE
      
      LINKER GENERATED COPY TABLES
      
      __TI_cinit_table @ 00000008 records: 1, size/record: 8, table size: 8
      	.fardata: load addr=00000010, load size=0000000d bytes, run addr=00000000, run size=0000000c bytes, compression=rle
      
      
      LINKER GENERATED HANDLER TABLE
      
      __TI_handler_table @ 00000000 records: 2, size/record: 4, table size: 8
      	index: 0, handler: __TI_decompress_rle24
      	index: 1, handler: __TI_decompress_none
      
      
      GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 
      
      address    name
      --------   ----
      000003a0   C$$EXIT
      00000008   __TI_CINIT_Base
      00000010   __TI_CINIT_Limit
      00000000   __TI_Handler_Table_Base
      00000008   __TI_Handler_Table_Limit
      UNDEFED    __TI_INITARRAY_Base
      UNDEFED    __TI_INITARRAY_Limit
      00000400   __TI_STACK_END
      00000400   __TI_STACK_SIZE
      00000000   __TI_STATIC_BASE
      UNDEFED    __TI_TLS_BLOCK_SIZE
      UNDEFED    __TI_TLS_INIT_Base
      UNDEFED    __TI_TLS_INIT_Limit
      UNDEFED    __TI_TLS_MAIN_THREAD_Base
      00000001   __TI_args_main
      00000660   __TI_cpp_init
      00000080   __TI_decompress_none
      00000380   __TI_decompress_rle
      00000180   __TI_decompress_rle24
      00000008   __TI_enable_exit_profile_output
      ffffffff   __TI_pprof_out_hndl
      ffffffff   __TI_prof_data_size
      ffffffff   __TI_prof_data_start
      000008e0   __TI_tls_block_size
      00000820   __TI_tls_init
      00000800   __TI_tls_main_thread_base
      000000a0   __TI_zero_init
      ffffffff   __binit__
      000007c0   __c6xabi_get_addr
      00000900   __c6xabi_get_tp
      ffffffff   __c_args__
      00000520   _args_main
      00000560   _auto_init_elf
      00000000   _c_int00
      00000000   _cleanup_ptr
      00000004   _dtors_ptr
      00000000   _stack
      000003a0   abort
      ffffffff   binit
      000006c0   copy_in
      000003c0   exit
      000001a8   main
      00000480   memcpy
      000001a0   testfunc
      
      
      GLOBAL SYMBOLS: SORTED BY Symbol Address 
      
      address    name
      --------   ----
      00000000   __TI_Handler_Table_Base
      00000000   __TI_STATIC_BASE
      00000000   _c_int00
      00000000   _cleanup_ptr
      00000000   _stack
      00000001   __TI_args_main
      00000004   _dtors_ptr
      00000008   __TI_CINIT_Base
      00000008   __TI_Handler_Table_Limit
      00000008   __TI_enable_exit_profile_output
      00000010   __TI_CINIT_Limit
      00000080   __TI_decompress_none
      000000a0   __TI_zero_init
      00000180   __TI_decompress_rle24
      000001a0   testfunc
      000001a8   main
      00000380   __TI_decompress_rle
      000003a0   C$$EXIT
      000003a0   abort
      000003c0   exit
      00000400   __TI_STACK_END
      00000400   __TI_STACK_SIZE
      00000480   memcpy
      00000520   _args_main
      00000560   _auto_init_elf
      00000660   __TI_cpp_init
      000006c0   copy_in
      000007c0   __c6xabi_get_addr
      00000800   __TI_tls_main_thread_base
      00000820   __TI_tls_init
      000008e0   __TI_tls_block_size
      00000900   __c6xabi_get_tp
      ffffffff   __TI_pprof_out_hndl
      ffffffff   __TI_prof_data_size
      ffffffff   __TI_prof_data_start
      ffffffff   __binit__
      ffffffff   __c_args__
      ffffffff   binit
      UNDEFED    __TI_INITARRAY_Base
      UNDEFED    __TI_INITARRAY_Limit
      UNDEFED    __TI_TLS_BLOCK_SIZE
      UNDEFED    __TI_TLS_INIT_Base
      UNDEFED    __TI_TLS_INIT_Limit
      UNDEFED    __TI_TLS_MAIN_THREAD_Base
      
      [44 symbols]
      

      
      
   2. When running from SPI boot on the EVM
      
      
   3. When running from SPI boot on the custom hardware:
      The PC appears to be stuck in the RBL.
   4. To me, this basically proves that the custom hardware is not getting the proper information to boot.

The only thing I am left with is that the flash memory is not getting written to properly or not being read properly. 

1. This could be something to do with the multitude of steps(tools) to create a properly configured image to load onto the hardware.  I have just been blindly following the EVM's example to get the programming image.  I do not know if there was some hardware specific configuration within these tools.
2. A problem with the NORwriter tool loading the memory.
3. Data not being read correctly from the memory by the RBL.

Any assistance is appreciated.

I have been trying to rebuild the NOR flashwriter that is included with the PDK, but I am having trouble getting the makefile to properly run.  I am not very familiar with the command line environment to configure/run the compiler/linker.  Do you have any instructions on how to rebuild the NOR flashwriter? 

• The NOR writer make file was located by default in C:\ti\pdk_c665x_2_0_16\packages\ti\boot\writer\nor\evmc6657l\build
• I have tried to run the makefile under MinGW but something is not setup correctly.
  

  sut@KCK /c/ti/pdk_c665x_2_0_16/packages
  $ source pdksetupenv.sh
  /c/ti/pdk_c665x_2_0_16/packages
  /c/ti/pdk_c665x_2_0_16/packages
  **************************************************************************
  Environment Configuration:
  **************************************************************************
      SDK_INSTALL_PATH        : /c/ti
      PDK_INSTALL_PATH        : /c/ti/pdk_c665x_2_0_16/packages
      PDK_SOC                 : c665x
      PDK_VERSION             : 2_0_16
      RULES_MAKE              : /c/ti/pdk_c665x_2_0_16/packages/ti/build/Rules.make
  **************************************************************************
  
  sut@KCK /c/ti/pdk_c665x_2_0_16/packages
  $ cd C:/ti/pdk_c665x_2_0_16/packages/ti/boot/writer/nor/evmc6657l/build
  
  sut8@KCK /c/ti/pdk_c665x_2_0_16/packages/ti/boot/writer/nor/evmc6657l/build
  $ gmake
  gmake: *** No rule to make target '/oe/bld/build-CORTEX_1/arago-tmp-external-arm-toolchain/work/c665x_evm-linux-gnueabi/flashwriters-rtos/git-r11/recipe-sysroot-native/usr/share/ti/cgt-c6x/include/stdlib.h', needed by 'src/norwriter.obj'.  Stop.
  
  sut@KCK /c/ti/pdk_c665x_2_0_16/packages/ti/boot/writer/nor/evmc6657l/build
  $

Thanks,

Brad,

Point no: 1

In your spiboot.map, it still shows DDR.... Which means, in spiboot.cmd, the DDR was not removed completely...

 DDR                   80000000   00002000  00000000  00002000  RWIX

---

Point no: 2

L2_DATA : origin = 0x800000, length = 0xff000 --- This memory segment is also missing in your .cmd

----

Point no: 3

ENTRY POINT SYMBOL: "_c_int00"  address: 00000000  - Entry address cannot be zero... It should point to the L2 memory...

---

 Point no : 4

In your spiboot.map, it failed to alloate the sections ???... It should allocate the sections like .text, .stack, .fardata inside the L2_data memory, right?

SECTION ALLOCATION MAP

output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.fardata 0 00000000 0000000c FAILED TO ALLOCATE
.cinit 0 00000000 0000001d FAILED TO ALLOCATE
.stack 0 00000000 00000400 FAILED TO ALLOCATE
.text 0 00000000 00000920 FAILED TO ALLOCATE

----------------------------------------------------------------------------------------------

1. Please post your SPIboot.cmd, while running in the internal memory.

2. Please post your spiboot.map 

2. Please post your spiboot.c for your case 4.

--

Re-do the test by using the spiboot.cmd ( given below ) and spiboot.c ( given below )  on your custom board.

This time, your custom hardware should boot successfully with L2 internal memory.

/* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "tiboot.h"
#include "platform.h"

#define GPIO_BASE (0x2320000)
#define GPIO_DIR_OFFSET (0x10)
#define GPIO_SETDATA_OFFSET (0x18)
#define GPIO_CLEARDATA_OFFSET (0x1C)

void testfunc();

void testfunc()
{

    while (1)
    {
        asm("   IDLE");

    }
}

#if 1
void main(void)
{

    volatile uint32_t *reg_val;

     reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
     // configure as output pin -- write 0 to the Direction register
     *reg_val &= ~ (1 << 8);


     reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
     // Write value 1 in the set data register, so that Out data register will be 1
     *reg_val |= (1 << 8);
    testfunc();


}
#endif

	

spiboot.obj

-c
-a
-stack 0x400

MEMORY
{
    L2MAGIC   :  origin = 0x8ffffc, length = 0x4
	L2_DATA   :  origin = 0x800000,   length = 0xff000
}


SECTIONS
{
 	.stack > L2_DATA
	.msmc  > L2_DATA
	.data  > L2_DATA
	.far   > L2_DATA
	.text  > L2_DATA
	.const > L2_DATA
	.cinit > L2_DATA
	.lmagic > L2MAGIC
	

}

Regards

Shankari G

Sorry for that, as I was re-creating the test to document the results for you, I missed the error in the compile. (Working from the command line is not my forte anymore, I prefer working within the development environment (ie. red flags in the Problems section draw my attention)

Try two for presenting the data you requested.

• Current spiboot.cmd
  

  spiboot.obj
  
  -c
  -a
  -stack 0x400
  
  MEMORY
  {
  	L2MAGIC : origin = 0x8ffffc, length = 0x4
  	L2_DATA : origin = 0x800000, length = 0xff000
  }
  
  
  SECTIONS
  {
  //    .emif4Cfg > DDR_CFG
  
  	.stack > L2_DATA
  	.msmc  > L2_DATA
  	.data  > L2_DATA
  	.far   > L2_DATA
  	.text  > L2_DATA
  	.const > L2_DATA
  	.cinit > L2_DATA
  	.lmagic > L2MAGIC
  	
  
  }
  
  

• Current spiboot.c
  

  /* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   *
   *
   *  Redistribution and use in source and binary forms, with or without
   *  modification, are permitted provided that the following conditions
   *  are met:
   *
   *    Redistributions of source code must retain the above copyright
   *    notice, this list of conditions and the following disclaimer.
   *
   *    Redistributions in binary form must reproduce the above copyright
   *    notice, this list of conditions and the following disclaimer in the
   *    documentation and/or other materials provided with the
   *    distribution.
   *
   *    Neither the name of Texas Instruments Incorporated nor the names of
   *    its contributors may be used to endorse or promote products derived
   *    from this software without specific prior written permission.
   *
   *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
   *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
  
  #include <stdio.h>
  #include <string.h>
  #include <stdint.h>
  #include "tiboot.h"
  #include "platform.h"
  #if 0
  #pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
  const BOOT_EMIF4_TBL_T  emif4Cfg =  {
  
      BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
      BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
      BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
      BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
      BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
      BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
  	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
  	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,
  
      BOOT_EMIF_ENABLE_SLSW_config0 | \
  	BOOT_EMIF_ENABLE_SLSW_config6 | \
  	BOOT_EMIF_ENABLE_SLSW_config7 | \
  	BOOT_EMIF_ENABLE_SLSW_config8 | \
  	BOOT_EMIF_ENABLE_SLSW_config9 | \
  	BOOT_EMIF_ENABLE_SLSW_config10 | \
  	BOOT_EMIF_ENABLE_SLSW_config18 | \
  	BOOT_EMIF_ENABLE_SLSW_config19 | \
  	BOOT_EMIF_ENABLE_SLSW_config20 | \
  	BOOT_EMIF_ENABLE_SLSW_config22 | \
  	BOOT_EMIF_ENABLE_SLSW_config12 | \
  	BOOT_EMIF_ENABLE_SLSW_config23 | \
  	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
      0,      /* Config select lsw  */
      
      3,      /* pllPrediv  */
      40,     /* pllMult    */
      2,      /* pllPostDiv */
  
      0x62477AB2,  /* sdRamConfig */
      0,           /* sdRamConfig2, dont care*/
      0x0000144F,  /* sdRamRefreshCtl  */
      0x1333780C,  /* sdRamTiming1 */
      0x30717FE3,  /* sdRamTiming2 */
      0x559F86AF,  /* sdRamTiming3 */
  
      0,           /* lpDdrNvmTiming, dont care */
      0,           /* powerManageCtl, dont care */
      0,           /* iODFTTestLogic, dont care */
      0,           /* performCountCfg, dont care */
      0,           /* performCountMstRegSel, dont care */
      0,           /* readIdleCtl, dont care */
      0,           /* sysVbusmIntEnSet, dont care */
      0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
      0,           /* tempAlterCfg, dont care */
  
      0x0010010F,  /* ddrPhyCtl1 */
  
      0,           /* ddrPhyCtl2, dont care */
      0,           /* priClassSvceMap, dont care */
      0,           /* mstId2ClsSvce1Map, dont care */
      0,           /* mstId2ClsSvce2Map, dont care */
      0,           /* eccCtl, dont care */
      0,           /* eccRange1, dont care */
      0,           /* eccRange2, dont care */
      0,           /* rdWrtExcThresh, dont care */
  
      0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
      0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
      0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
      0, 0, 0, 0, 0, 0, 0, 0,
      
      0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0
  };
  #endif
  
  #define GPIO_BASE (0x2320000)
  #define GPIO_DIR_OFFSET (0x10)
  #define GPIO_SETDATA_OFFSET (0x18)
  #define GPIO_CLEARDATA_OFFSET (0x1C)
  
  void testfunc();
  
  void testfunc()
  {
  
      while (1)
      {
          asm("   IDLE");
  
      }
  }
  
  void main(void)
  {
  
      volatile uint32_t *reg_val;
  
       reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
       // configure as output pin -- write 0 to the Direction register
       *reg_val &= ~ (1 << 8);
  
  
       reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
       // Write value 1 in the set data register, so that Out data register will be 1
       *reg_val |= (1 << 8);
  
      testfunc();
  
  
  }
  

• Current spiboot.map
  

  ******************************************************************************
                 TMS320C6x Linker PC v7.4.24                     
  ******************************************************************************
  >> Linked Thu Oct 20 01:59:07 2022
  
  OUTPUT FILE NAME:   <spiboot.out>
  ENTRY POINT SYMBOL: "_c_int00"  address: 00800680
  
  
  MEMORY CONFIGURATION
  
           name            origin    length      used     unused   attr    fill
  ----------------------  --------  ---------  --------  --------  ----  --------
    L2_DATA               00800000   000ff000  00000d4c  000fe2b4  RWIX
    L2MAGIC               008ffffc   00000004  00000000  00000004  RWIX
  
  
  SEGMENT ALLOCATION MAP
  
  run origin  load origin   length   init length attrs members
  ----------  ----------- ---------- ----------- ----- -------
  00800000    00800000    00000920   00000920    r-x
    00800000    00800000    00000920   00000920    r-x .text
  00800920    00800920    00000400   00000000    rw-
    00800920    00800920    00000400   00000000    rw- .stack
  00800d20    00800d20    0000000c   0000000c    rw-
    00800d20    00800d20    0000000c   0000000c    rw- .fardata
  00800d30    00800d30    00000020   00000020    r--
    00800d30    00800d30    00000020   00000020    r-- .cinit
  
  
  SECTION ALLOCATION MAP
  
   output                                  attributes/
  section   page    origin      length       input sections
  --------  ----  ----------  ----------   ----------------
  .text      0    00800000    00000920     
                    00800000    00000180     rts6600_elf.lib : copy_decompress_rle.obj (.text:__TI_decompress_rle_core)
                    00800180    00000100                     : autoinit.obj (.text:_auto_init_elf)
                    00800280    00000100                     : cpy_tbl.obj (.text:copy_in)
                    00800380    000000e0                     : copy_zero_init.obj (.text:decompress:ZI:__TI_zero_init)
                    00800460    000000c0                     : exit.obj (.text:exit)
                    00800520    000000c0                     : tls.obj (.text:tls:init:__TI_tls_init)
                    008005e0    000000a0                     : memcpy64.obj (.text:memcpy)
                    00800680    00000080                     : boot.obj (.text:_c_int00)
                    00800700    00000060                     : cpp_init.obj (.text:__TI_cpp_init)
                    00800760    00000060     spiboot.obj (.text)
                    008007c0    00000040     rts6600_elf.lib : args_main.obj (.text:_args_main)
                    00800800    00000040                     : tls.obj (.text:tls:get_addr:__c6xabi_get_addr)
                    00800840    00000020                     : exit.obj (.text:abort)
                    00800860    00000020                     : copy_decompress_none.obj (.text:decompress:none:__TI_decompress_none)
                    00800880    00000020                     : copy_decompress_rle.obj (.text:decompress:rle24:__TI_decompress_rle24)
                    008008a0    00000020                     : copy_decompress_rle.obj (.text:decompress:rle:__TI_decompress_rle)
                    008008c0    00000020                     : tls.obj (.text:tls:block_size:__TI_tls_block_size)
                    008008e0    00000020                     : tls_get_tp.obj (.text:tls:get_tp)
                    00800900    00000020                     : tls.obj (.text:tls:main_base:__TI_tls_main_thread_base)
  
  .stack     0    00800920    00000400     UNINITIALIZED
                    00800920    00000008     rts6600_elf.lib : boot.obj (.stack)
                    00800928    000003f8     --HOLE--
  
  .fardata   0    00800d20    0000000c     
                    00800d20    0000000c     rts6600_elf.lib : exit.obj (.fardata)
  
  .cinit     0    00800d30    00000020     
                    00800d30    0000000d     (.cinit..fardata.load) [load image, compression = rle]
                    00800d3d    00000003     --HOLE-- [fill = 0]
                    00800d40    00000008     (__TI_handler_table)
                    00800d48    00000008     (__TI_cinit_table)
  
  
  LINKER GENERATED COPY TABLES
  
  __TI_cinit_table @ 00800d48 records: 1, size/record: 8, table size: 8
  	.fardata: load addr=00800d30, load size=0000000d bytes, run addr=00800d20, run size=0000000c bytes, compression=rle
  
  
  LINKER GENERATED HANDLER TABLE
  
  __TI_handler_table @ 00800d40 records: 2, size/record: 4, table size: 8
  	index: 0, handler: __TI_decompress_rle24
  	index: 1, handler: __TI_decompress_none
  
  
  GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 
  
  address    name
  --------   ----
  00800840   C$$EXIT
  00800d48   __TI_CINIT_Base
  00800d50   __TI_CINIT_Limit
  00800d40   __TI_Handler_Table_Base
  00800d48   __TI_Handler_Table_Limit
  UNDEFED    __TI_INITARRAY_Base
  UNDEFED    __TI_INITARRAY_Limit
  00800d20   __TI_STACK_END
  00000400   __TI_STACK_SIZE
  00000000   __TI_STATIC_BASE
  UNDEFED    __TI_TLS_BLOCK_SIZE
  UNDEFED    __TI_TLS_INIT_Base
  UNDEFED    __TI_TLS_INIT_Limit
  UNDEFED    __TI_TLS_MAIN_THREAD_Base
  00000001   __TI_args_main
  00800700   __TI_cpp_init
  00800860   __TI_decompress_none
  008008a0   __TI_decompress_rle
  00800880   __TI_decompress_rle24
  00800d28   __TI_enable_exit_profile_output
  ffffffff   __TI_pprof_out_hndl
  ffffffff   __TI_prof_data_size
  ffffffff   __TI_prof_data_start
  008008c0   __TI_tls_block_size
  00800520   __TI_tls_init
  00800900   __TI_tls_main_thread_base
  00800380   __TI_zero_init
  ffffffff   __binit__
  00800800   __c6xabi_get_addr
  008008e0   __c6xabi_get_tp
  ffffffff   __c_args__
  008007c0   _args_main
  00800180   _auto_init_elf
  00800680   _c_int00
  00800d20   _cleanup_ptr
  00800d24   _dtors_ptr
  00800920   _stack
  00800840   abort
  ffffffff   binit
  00800280   copy_in
  00800460   exit
  00800768   main
  008005e0   memcpy
  00800760   testfunc
  
  
  GLOBAL SYMBOLS: SORTED BY Symbol Address 
  
  address    name
  --------   ----
  00000000   __TI_STATIC_BASE
  00000001   __TI_args_main
  00000400   __TI_STACK_SIZE
  00800180   _auto_init_elf
  00800280   copy_in
  00800380   __TI_zero_init
  00800460   exit
  00800520   __TI_tls_init
  008005e0   memcpy
  00800680   _c_int00
  00800700   __TI_cpp_init
  00800760   testfunc
  00800768   main
  008007c0   _args_main
  00800800   __c6xabi_get_addr
  00800840   C$$EXIT
  00800840   abort
  00800860   __TI_decompress_none
  00800880   __TI_decompress_rle24
  008008a0   __TI_decompress_rle
  008008c0   __TI_tls_block_size
  008008e0   __c6xabi_get_tp
  00800900   __TI_tls_main_thread_base
  00800920   _stack
  00800d20   __TI_STACK_END
  00800d20   _cleanup_ptr
  00800d24   _dtors_ptr
  00800d28   __TI_enable_exit_profile_output
  00800d40   __TI_Handler_Table_Base
  00800d48   __TI_CINIT_Base
  00800d48   __TI_Handler_Table_Limit
  00800d50   __TI_CINIT_Limit
  ffffffff   __TI_pprof_out_hndl
  ffffffff   __TI_prof_data_size
  ffffffff   __TI_prof_data_start
  ffffffff   __binit__
  ffffffff   __c_args__
  ffffffff   binit
  UNDEFED    __TI_INITARRAY_Base
  UNDEFED    __TI_INITARRAY_Limit
  UNDEFED    __TI_TLS_BLOCK_SIZE
  UNDEFED    __TI_TLS_INIT_Base
  UNDEFED    __TI_TLS_INIT_Limit
  UNDEFED    __TI_TLS_MAIN_THREAD_Base
  
  [44 symbols]
  

• Load Results
  
• Booting custom hardware with SPI boot configuration and connecting debugger after boot has occurred
  
  No success.  As you can see the PC is still within the RBL code area!

Do you have any instructions on how to rebuild the NOR flashwriter? 

BradS said:

I am questioning the NORwriter tool because when running the app it take significantly longer for the NORwriter to complete it's write and verification when running on the custom hardware. (i.e. EVM completes quickly <5sec and the custom hardware completes in 20-30sec)

Brad,

1. Using CCS, Do the register dump when the EVM uses the NOR_writer to flash the NOR memory - < 5sec

2. Using CCS, Do the register dump when the custom hardware uses the NOR-Writer to flash the NOR-memory - 20 -30 sec

3. Compare 1 and 2 and identify the difference in set-of-register values which are particular for SPI related, PLL etc.

Try modifying those particular register values in your saratoga_1333.gel ( according to the SPI parts used in your custom hardware ) and check the time is reduced from 20 -30 sec..

BradS said:

Do you have any instructions on how to rebuild the NOR flashwriter? 

I have to check. 

I have never-ever rebuilt the nor-writer as the necessity never arises, when it worked properly on the EVM..

Regards

Shankari G

Brad,

The following are the steps to re-build the NOR-writer

Regards

Shankari G

Brad,

I am able to build the NOR-writer. Those steps are captured and posted in my previous post, above...

Are you able to succeed re-building the NOR-Writer?

--

If yes, the next step is this ----> Modify the NOR_WRITER code for your custom hardware

1. In NOR-Writer-Source code, the SPI-NOR parts used is "PLATFORM_DEVID_NORN25Q128". Check and change the appropriate SPI_NOR parts used in your custom hardware.

2. In NOR-Writer-Source code --- > nor_init () --- >evmc665x_nor.c in platform_lib_evmc6657l/src --- modify the SPI interface section and NOR memory section according to your custom- hardware

NOR_STATUS 
nor_init
(   
    void
)
{
    NOR_STATUS          ret;
    uint8_t               idcode[3];     /* Initialize the SPI interface */

    /* Claim the SPI controller */
    spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);
    
    /* Read the ID codes */
    ret = spi_cmd(SPI_NOR_CMD_RDID, idcode, sizeof(idcode));
    if (ret) 
    {
        IFPRINT (platform_write( "nor_init: Error in reading the idcode\n"));
        spi_release();
        platform_errno = PLATFORM_ERRNO_NOR;
        return NOR_EFAIL;
    }
     
    IFPRINT (platform_write("SF: Got idcode %02x %02x %02x\n", idcode[0], idcode[1], idcode[2]));

    if ((idcode[0] != SPI_NOR_MANID_MICRON) && (idcode[0] != SPI_NOR_MANID_MACRONIX)) {
        /* Expected Manufacturer ID does not match */
        spi_release();
        platform_errno = PLATFORM_ERRNO_BADFLASHDEV;
        return NOR_EFAIL;
    }
       
    spi_release();
    return NOR_EOK; 
}

3. evmc665x_spi.c --> spi_claim() in platform_lib_evmc6657l/src 

3. 

spi_claim
(
    uint32_t      cs,
    uint32_t      freq
)
{
    uint32_t scalar;

    PLIBSPILOCK()

    /* Enable the SPI hardware */
    SPI_SPIGCR0 = CSL_SPI_SPIGCR0_RESET_IN_RESET;
    spi_delay (2000);
    SPI_SPIGCR0 = CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET;

    /* Set master mode, powered up and not activated */
    SPI_SPIGCR1 =   (CSL_SPI_SPIGCR1_MASTER_MASTER << CSL_SPI_SPIGCR1_MASTER_SHIFT)   |
                    (CSL_SPI_SPIGCR1_CLKMOD_INTERNAL << CSL_SPI_SPIGCR1_CLKMOD_SHIFT);
    
    
    /* CS0, CS1, CLK, Slave in and Slave out are functional pins */
    if (cs == 0) {
        SPI_SPIPC0 =    (CSL_SPI_SPIPC0_SCS0FUN0_SPI << CSL_SPI_SPIPC0_SCS0FUN0_SHIFT) |
                        (CSL_SPI_SPIPC0_CLKFUN_SPI << CSL_SPI_SPIPC0_CLKFUN_SHIFT)     |
                        (CSL_SPI_SPIPC0_SIMOFUN_SPI << CSL_SPI_SPIPC0_SIMOFUN_SHIFT)   |
                        (CSL_SPI_SPIPC0_SOMIFUN_SPI << CSL_SPI_SPIPC0_SOMIFUN_SHIFT);
    } else if (cs == 1) {
        SPI_SPIPC0 =    ((CSL_SPI_SPIPC0_SCS0FUN1_SPI << CSL_SPI_SPIPC0_SCS0FUN1_SHIFT) |
                        (CSL_SPI_SPIPC0_CLKFUN_SPI << CSL_SPI_SPIPC0_CLKFUN_SHIFT)     |
                        (CSL_SPI_SPIPC0_SIMOFUN_SPI << CSL_SPI_SPIPC0_SIMOFUN_SHIFT)   |
                        (CSL_SPI_SPIPC0_SOMIFUN_SPI << CSL_SPI_SPIPC0_SOMIFUN_SHIFT)) & 0xFFFF;
    }
    
    /* setup format */
    scalar = ((SPI_MODULE_CLK / freq) - 1 ) & 0xFF;

    if ( cs == 0) {
        SPI_SPIFMT0 =   (8 << CSL_SPI_SPIFMT_CHARLEN_SHIFT)               |
                        (scalar << CSL_SPI_SPIFMT_PRESCALE_SHIFT)                      |
                        (CSL_SPI_SPIFMT_PHASE_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT)     |
                        (CSL_SPI_SPIFMT_POLARITY_LOW << CSL_SPI_SPIFMT_POLARITY_SHIFT) |
                        (CSL_SPI_SPIFMT_SHIFTDIR_MSB << CSL_SPI_SPIFMT_SHIFTDIR_SHIFT);
    }else if ( cs == 1) {
        SPI_SPIFMT0 =   (16 << CSL_SPI_SPIFMT_CHARLEN_SHIFT)               |
                        (scalar << CSL_SPI_SPIFMT_PRESCALE_SHIFT)                      |
                        (CSL_SPI_SPIFMT_PHASE_NO_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT)     |
                        (CSL_SPI_SPIFMT_POLARITY_LOW << CSL_SPI_SPIFMT_POLARITY_SHIFT) |
                        (CSL_SPI_SPIFMT_SHIFTDIR_MSB << CSL_SPI_SPIFMT_SHIFTDIR_SHIFT);
    }
    
    /* hold cs active at end of transfer until explicitly de-asserted */
    data1_reg_val = (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
                    (0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT);
     if (cs == 0) {
         SPI_SPIDAT1 =   (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
                         (0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT);
     } 

    /* including a minor delay. No science here. Should be good even with
    * no delay
    */
    if (cs == 0) {
        SPI_SPIDELAY =  (8 << CSL_SPI_SPIDELAY_C2TDELAY_SHIFT) |
                        (8 << CSL_SPI_SPIDELAY_T2CDELAY_SHIFT);
        /* default chip select register */
        SPI_SPIDEF  = CSL_SPI_SPIDEF_RESETVAL;        
    } else if (cs == 1) {    
        SPI_SPIDELAY =  (6 << CSL_SPI_SPIDELAY_C2TDELAY_SHIFT) |
                        (3 << CSL_SPI_SPIDELAY_T2CDELAY_SHIFT);
    }
    
    /* no interrupts */
    SPI_SPIINT0 = CSL_SPI_SPIINT0_RESETVAL;
    SPI_SPILVL  = CSL_SPI_SPILVL_RESETVAL;

    /* enable SPI */
    SPI_SPIGCR1 |= ( CSL_SPI_SPIGCR1_ENABLE_ENABLE << CSL_SPI_SPIGCR1_ENABLE_SHIFT );

    if (cs == 1) {
        SPI_SPIDAT0 = 1 << 15; 
        spi_delay (10000);        
        /* Read SPIFLG, wait untill the RX full interrupt */
        if ( (SPI_SPIFLG & (CSL_SPI_SPIFLG_RXINTFLG_FULL<<CSL_SPI_SPIFLG_RXINTFLG_SHIFT)) ) {                
            /* Read one byte data */
            scalar = SPI_SPIBUF & 0xFF;
            /* Clear the Data */
            SPI_SPIBUF = 0;
        }
        else {
            /* Read one byte data */
            scalar = SPI_SPIBUF & 0xFF;
            return SPI_EFAIL;
        }
    }
    return SPI_EOK;
}

Regards

Shankari G

Yes, I have been able to build the NOR-Writer code.  I have modified it to report what the unit is sending and receiving from the memory. 

I instrumented the SPI lines to validate the communications between the C6657 and the SPI memory on the custom hardware as close to the C6657 as possible (ie. inline termination resistor).  In looking at this data I can see the read and write transactions. (i.e. CS0 goes low, CLK toggles, MOSI and MISO change appropriately, CS0 returns high).  The data transferred over the link appears correct, both in what is transmitted to the memory and from the memory.

Now knowing that the probes are properly connected and working, I changed the custom hardware's bootmode pins to SPI boot and repowered the board.  After the C6657 is released from reset I can see the SPI clock line is generating repeated groups of 8 clock pulses.  However, the chip select line is always high (i.e. inactive)!!!!  This precludes the ability of the SPI memory to return the appropriate data for booting the processor.

I have now double checks the reset lines just to make sure the unit is getting out of reset properly.  The resets are deactivated in the following order. LReset*(always high), Reset*, 100mS delay, POR*, 100mS delay, and then ResetFull*.  ResetStatus goes high 5mS after ResetFull* goes active.  Also I have validated that the CoreClk is present for a long time before ResetFull goes inactive.

(i.e. It appears that the processor is coming out of reset properly)

Question:

1. Any idea of what could cause this?

Over the weekend I hope to recreate these tests using the EVM to compare operation between the two boards.

Additional Research Questions:

I was reread the section of the datasheet on the bootmode configuration, SPRS814D section 6.28.2.7 SPI Boot Device Configuration, I have a couple clarifications on this.

•  Bit 10  4, 5  pin mode configuration. I haven't found any additional documentation on this but I think this is what is meant by the two modes.  Are the following two statements correct?
  • In 4-pin mode: During SPI boot the C6657 takes control of and drives only the SPI CLK, MOSI, MISO, and CS0.
  • In 5-pin mode: During SPI boot the C6657 takes control of and drives only the SPI CLK, MOSI, MISO, CS0, and CS1.
• Bits 7:8
  • The EVM uses this as 00b, but the data sheet in table 6-76 appears to state that this is "not used"
    • Does this just mean that both chip selects are supposed to activated during boot or is this a not recommended configuration for the bootloader?
  • Switching these to 01b CS0 did not change the boot operation of the custom hardware.

This is getting very frustrating...

Maybe it is time to 'throw in the towel' on trying to get the SPI direct boot to operate and move on to trying to create a minimal boot application for the I2C EEPROM???

In thinking about this issue (i.e. the RBL does not appear to be properly loading code directly from the SPI port)... Earlier in the discussion I found that after attempting to boot the custom hardware from the SPI and then connecting the debugger, the processor was executing code from within the RBL.  Maybe the location the code was stuck at could give me clues as to what the issue is with booting directly from the SPI.  (i.e. the PC was at 0x20B11B52: what is the RBL attempting to do around this location?)  

Brad,

That's good that you tested the memory- read and write..

Over the weekend I did some useful experiment which will help you.....

BradS said:

Question:

1. Any idea of what could cause this?

Over the weekend I hope to recreate these tests using the EVM to compare operation between the two boards.

I guess the cause is most likely found.

But you may have to confirm me, by running your SPI-NOR in the custom hardware at lower frequency. ( Will post you the experiment steps shortly. Let me post the steps by EOD - 7 pm IST)

BradS said:

In thinking about this issue (i.e. the RBL does not appear to be properly loading code directly from the SPI port)... Earlier in the discussion I found that after attempting to boot the custom hardware from the SPI and then connecting the debugger, the processor was executing code from within the RBL.  Maybe the location the code was stuck at could give me clues as to what the issue is with booting directly from the SPI.  (i.e. the PC was at 0x20B11B52: what is the RBL attempting to do around this location?)  

It is not the RBL which is causing issue. The major cause is this.... Please give more focus...

I made an important experiment that the SPI in the EVM works on the frequency set by the C6657-gel (-high frequency ) and the RBL( -low frequency).

    ----> ( RBL with PLLM value as "PLL_pllm - 0x0000001F " and the gel with PLLM value as "PLL_pllm - 0x00000013 ")

But the spi in your custom hardware works on the frequency set by the saratoga_1333.gel but doesnot works with the low frequency set by the RBL during minimal configuration.

===========

C6657-EVM

===========

Custom hardware

===========

( Brad, find this value ) * - Feed the same PLLM value on your gel file and check whether the SPI works. If it doesnot work, which means, the SPI doesnot work at the frequency set by the RBL. This has to be debugged by your hardware team on your custom board......

In general, if the SPI in the custom hardware doesnot work for the low frequency, it will be a problem irrespective of your booting choice.. ( Please consider, as it may affect in your later point of development )   

---

BradS said:

Maybe it is time to 'throw in the towel' on trying to get the SPI direct boot to operate and move on to trying to create a minimal boot application for the I2C EEPROM???

After you confirm the SPI works with PLLM value 0x0000001F, let us move on to the IBL + app.

Regards

Shankari G

I am not saying that the RBL is the issue.  I am trying to understand the operation of the RBL to diagnose the issue.  If you know exactly what the RBL is doing, the fact that the PC is executing code around PC=0x20B11B52 would give you insight into what the RBL was attempting to do and/or why the RBL did not execute properly (i.e. missing configuration).

Shankari G said:

Custom hardware

===========

Tests	saratoga_1333.gel	RBL
Custom hardware	C6657 gel with all register configuration  PLLM - value -	With minimal configuration PLLM - value -  ( Brad has to confirm that the value is 0x0000001F ) *
Boot-Result	Works fine and boots the app	Doesnot work
Conclusion	SPI works with PLLM value - 0x00000013	Feed the PLLM value - 0x0000001F in the saratoga_1333.gel, and check whether the SPI works at low frequency.

( Brad, find this value ) * - Feed the same PLLM value on your gel file and check whether the SPI works. If it doesnot work, which means, the SPI doesnot work at the frequency set by the RBL. This has to be debugged by your hardware team on your custom board......

1. If looks like you are asking me to perform a two part test.
   1. Change the value of the PLLM register in my gel file to 0x1F and attempt to communicate with the SPI NOR memory. (i.e. load the NORwriter program and load something into the SPI NOR flash.
   2. Execute the RBL after configuring the the PLLM register.
      1. How is this done?

Thanks,

Brad

Brad,

Let us setup a call today.

Is it ok to have a call at 4 pm IST? 

Regards

Shankari G

Brad,

If it is a short notice, we shall have a call at 2 pm IST - 27-10-2022.

Regards

Shankari G

I will plan on being in the early tomorrow (OCT 27 by 3am CDT which should be OCT 27 1:30AM IST).  Please reschedule the call for 2PM IST OCT 27th.

Thanks,

Brad

OK, Brad.

Will schedule and send the invite for 2 PM IST on 27th OCT.

---

Meanwhile, let us do this...

These are the steps for the above experiment.

===================================

1. Download this gel file ( I have modified ) - ( given below)

2. Run in your custom hardware.

3. Share the gel-console-output in a txt format ( Not as a snapshot, please )

4. Generate register dump-- Options-->View-->Register-->right-click-->export-->choose_name_and_path with .txt as extension -->selectall-->click-OK

5. Send this register dump in a txt format.

6. Load the NOR-writer.out.

7.Flash the app.dat ( given below)

8. Share the console message of "Flashed successfully" .( If get errors, please share that too)

9. change the boot settings into SPI-NOR.

10. Share the PC counter value.

11. Have a nice day!. Bye, Brad.

---

saratoga_1333_26oct.gel

2671.app.dat

Regards

Shankari G

3. Gel file Output

C66xx_0: GEL Output: ***  Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: DEVSTAT 0x00000501 
C66xx_0: GEL Output: Bootmode = 0x00000000 
C66xx_0: GEL Output: File: Saratoga_1333.gel
C66xx_0: GEL Output: File Ver is 1.0 
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache... 
C66xx_0: GEL Output: L1P = 32K   
C66xx_0: GEL Output: L1D = 32K   
C66xx_0: GEL Output: L2 = ALL SRAM   
C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL in Bypass ... 
C66xx_0: GEL Output: pll_multiplier = (31) 
C66xx_0: GEL Output: PLL1_PLLM = (31) 
C66xx_0: GEL Output: PLL1_CMD = (1) 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1600.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 533.333313 MHz, SYSCLK5 = 320.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 25.0 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: Mult: 79  Divider:2
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output: DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: W:(0x80000100) ...
C66xx_0: GEL Output: W:(0x80000200) ...
C66xx_0: GEL Output: W:(0x80000300) ...
C66xx_0: GEL Output: R:(0x80000100) ...
C66xx_0: GEL Output: R:(0x80000200) ...
C66xx_0: GEL Output: R:(0x80000300) ...
C66xx_0: GEL Output: WC:(0x80000100) ...
C66xx_0: GEL Output: WC:(0x80000200) ...
C66xx_0: GEL Output: WC:(0x80000300) ...
C66xx_0: GEL Output: RC:(0x80000100) ...
C66xx_0: GEL Output: RC:(0x80000200) ...
C66xx_0: GEL Output: RC:(0x80000300) ...
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR3 Initialization completed(Retry Cnt:0) ...
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done 
C66xx_0: GEL Output: Global Default Setup... Done.

4. Register Dump

521177 102
R PC 0x0000000B 0x20B00F70
R CLK 0x0000000B 0x00000000
R SP 0x0000000B 0x008FFA20
R FP 0x0000000B 0x008FFA20
R A0 0x0000000B 0x00000001
R A1 0x0000000B 0x00000001
R A2 0x0000000B 0x01000000
R A3 0x0000000B 0x01000000
R A4 0x0000000B 0x01845044
R A5 0x0000000B 0x0180010C
R A6 0x0000000B 0x00000018
R A7 0x0000000B 0x00000000
R A8 0x0000000B 0x00000000
R A9 0x0000000B 0x008EFD88
R A10 0x0000000B 0x008FFFFC
R A11 0x0000000B 0x01845044
R A12 0x0000000B 0x7F51A7D4
R A13 0x0000000B 0x10440175
R A14 0x0000000B 0xDF2CF838
R A15 0x0000000B 0x26CF4000
R A16 0x0000000B 0x008EFD80
R A17 0x0000000B 0x00000000
R A18 0x0000000B 0xC0072A48
R A19 0x0000000B 0x41811046
R A20 0x0000000B 0x1222052E
R A21 0x0000000B 0x1222052E
R A22 0x0000000B 0x3D8A4B54
R A23 0x0000000B 0x3D8A4B54
R A24 0x0000000B 0x60601088
R A25 0x0000000B 0x042A4C01
R A26 0x0000000B 0x57F7B4D7
R A27 0x0000000B 0x896912A0
R A28 0x0000000B 0x82C93508
R A29 0x0000000B 0x807A097F
R A30 0x0000000B 0xB6E9E729
R A31 0x0000000B 0x07A2E607
R B0 0x0000000B 0x01000000
R B1 0x0000000B 0x00000000
R B2 0x0000000B 0x00000000
R B3 0x0000000B 0x20B00F68
R B4 0x0000000B 0x02620140
R B5 0x0000000B 0x20B03420
R B6 0x0000000B 0x008EFF98
R B7 0x0000000B 0x00000000
R B8 0x0000000B 0x03FFFCF6
R B9 0x0000000B 0x8DB2DE79
R B10 0x0000000B 0x20B00000
R B11 0x0000000B 0xEEA7F29D
R B12 0x0000000B 0xA03A0116
R B13 0x0000000B 0xB98228A0
R B14 0x0000000B 0xA9060F02
R B15 0x0000000B 0x008FFA20
R B16 0x0000000B 0x20B0866C
R B17 0x0000000B 0x20B0A340
R B18 0x0000000B 0x02011A40
R B19 0x0000000B 0xFFFF9FBF
R B20 0x0000000B 0x40215022
R B21 0x0000000B 0x71B69AC9
R B22 0x0000000B 0x9004D450
R B23 0x0000000B 0x9DBF7F34
R B24 0x0000000B 0x42169022
R B25 0x0000000B 0x9F4FEFD7
R B26 0x0000000B 0x00040250
R B27 0x0000000B 0x10ED058B
R B28 0x0000000B 0x203810F0
R B29 0x0000000B 0xC6583E65
R B30 0x0000000B 0x22A8221E
R B31 0x0000000B 0x6E32FEDF
R ERP 0x0000000B 0x00000000
R ARP 0x0000000B 0x00000000
R DIER 0x0000000B 0x00000000
R ETSR 0x0000000B 0x00000000
R ControlRegisters_AMR 0x0000000B 0x00000000
R ControlRegisters_CSR 0x0000000B 0x15000101
R ControlRegisters_GFPGFR 0x0000000B 0x0700001D
R ControlRegisters_ICR 0x0000000B 0x00000000
R ControlRegisters_IER 0x0000000B 0x000001F3
R ControlRegisters_IFR 0x0000000B 0x00000000
R ControlRegisters_IRP 0x0000000B 0x00000000
R ControlRegisters_ISR 0x0000000B 0x00000000
R ControlRegisters_ISTP 0x0000000B 0x20B15C00
R ControlRegisters_NRP 0x0000000B 0x00000000
R ControlRegisters_PCE1 0x0000000B 0x20B00F70
R ControlRegisters_DNUM 0x0000000B 0x00000000
R ControlRegisters_ECR 0x0000000B 0x00000000
R ControlRegisters_EFR 0x0000000B 0x00000000
R ControlRegisters_GPLYA 0x0000000B 0x00000000
R ControlRegisters_GPLYB 0x0000000B 0x00000000
R ControlRegisters_IERR 0x0000000B 0x00000000
R ControlRegisters_ILC 0x0000000B 0x00000000
R ControlRegisters_ITSR 0x0000000B 0x00000000
R ControlRegisters_NTSR 0x0000000B 0x00000000
R ControlRegisters_REP 0x0000000B 0x00000000
R ControlRegisters_RILC 0x0000000B 0x00000000
R ControlRegisters_SSR 0x0000000B 0x00000000
R ControlRegisters_TSCH 0x0000000B 0x0B61B830
R ControlRegisters_TSCL 0x0000000B 0x00000000
R ControlRegisters_TSR 0x0000000B 0x00000001
R ControlRegisters_FADCR 0x0000000B 0x00000000
R ControlRegisters_FAUCR 0x0000000B 0x00000000
R ControlRegisters_FMCR 0x0000000B 0x00000000
R RegisterPairs_A1_A0 0x00000019 0x0000000100000001
R RegisterPairs_A3_A2 0x00000019 0x0100000001000000
R RegisterPairs_A5_A4 0x00000019 0x0180010C01845044
R RegisterPairs_A7_A6 0x00000019 0x0000000000000018
R RegisterPairs_A9_A8 0x00000019 0x008EFD8800000000
R RegisterPairs_A11_A10 0x00000019 0x01845044008FFFFC
R RegisterPairs_A13_A12 0x00000019 0x104401757F51A7D4
R RegisterPairs_A15_A14 0x00000019 0x26CF4000DF2CF838
R RegisterPairs_A17_A16 0x00000019 0x00000000008EFD80
R RegisterPairs_A19_A18 0x00000019 0x41811046C0072A48
R RegisterPairs_A21_A20 0x00000019 0x1222052E1222052E
R RegisterPairs_A23_A22 0x00000019 0x3D8A4B543D8A4B54
R RegisterPairs_A25_A24 0x00000019 0x042A4C0160601088
R RegisterPairs_A27_A26 0x00000019 0x896912A057F7B4D7
R RegisterPairs_A29_A28 0x00000019 0x807A097F82C93508
R RegisterPairs_A31_A30 0x00000019 0x07A2E607B6E9E729
R RegisterPairs_B1_B0 0x00000019 0x0000000001000000
R RegisterPairs_B3_B2 0x00000019 0x20B00F6800000000
R RegisterPairs_B5_B4 0x00000019 0x20B0342002620140
R RegisterPairs_B7_B6 0x00000019 0x00000000008EFF98
R RegisterPairs_B9_B8 0x00000019 0x8DB2DE7903FFFCF6
R RegisterPairs_B11_B10 0x00000019 0xEEA7F29D20B00000
R RegisterPairs_B13_B12 0x00000019 0xB98228A0A03A0116
R RegisterPairs_B15_B14 0x00000019 0x008FFA20A9060F02
R RegisterPairs_B17_B16 0x00000019 0x20B0A34020B0866C
R RegisterPairs_B19_B18 0x00000019 0xFFFF9FBF02011A40
R RegisterPairs_B21_B20 0x00000019 0x71B69AC940215022
R RegisterPairs_B23_B22 0x00000019 0x9DBF7F349004D450
R RegisterPairs_B25_B24 0x00000019 0x9F4FEFD742169022
R RegisterPairs_B27_B26 0x00000019 0x10ED058B00040250
R RegisterPairs_B29_B28 0x00000019 0xC6583E65203810F0
R RegisterPairs_B31_B30 0x00000019 0x6E32FEDF22A8221E
R HYPERLINK_rev 0x0000000B 0x4E901900
R HYPERLINK_ctl 0x0000000B 0x00000000
R HYPERLINK_sts 0x0000000B 0x00003004
R HYPERLINK_int_pri_vec 0x0000000B 0x80000000
R HYPERLINK_int_clr 0x0000000B 0x00000000
R HYPERLINK_int_set 0x0000000B 0x00000000
R HYPERLINK_sw_int 0x0000000B 0x00000000
R HYPERLINK_tx_sel_ctl 0x0000000B 0x00000000
R HYPERLINK_rx_sel_ctl 0x0000000B 0x00000000
R HYPERLINK_rx_priv_idx 0x0000000B 0x00000000
R HYPERLINK_rx_priv_val 0x0000000B 0x00000000
R HYPERLINK_rx_seg_idx 0x0000000B 0x00000000
R HYPERLINK_rx_seg_val 0x0000000B 0x00000000
R HYPERLINK_chip_id_ver 0x0000000B 0x0000B97A
R HYPERLINK_pwr 0x0000000B 0x07070007
R HYPERLINK_ecc_cntr 0x0000000B 0x00000000
R HYPERLINK_link_sts 0x0000000B 0x00000000
R HYPERLINK_int_ctl_idx 0x0000000B 0x00000000
R HYPERLINK_int_ctl_val 0x0000000B 0x00000000
R HYPERLINK_int_ptr_idx 0x0000000B 0x00000000
R HYPERLINK_int_ptr_val 0x0000000B 0x00000000
R HYPERLINK_serdes_ctl_sts1 0x0000000B 0x092E0000
R HYPERLINK_serdes_ctl_sts2 0x0000000B 0x00000000
R HYPERLINK_serdes_ctl_sts3 0x0000000B 0x00000000
R HYPERLINK_serdes_ctl_sts4 0x0000000B 0x00000000
R VCP_A_CFG_vcppid 0x0000000B 0x480A0000
R VCP_A_CFG_vcpexe 0x0000000B 0x00000000
R VCP_A_CFG_vcpend 0x0000000B 0x00000000
R VCP_A_CFG_vcpstat0 0x0000000B 0x00000010
R VCP_A_CFG_vcpstat1 0x0000000B 0x00000000
R VCP_A_CFG_vcperr 0x0000000B 0x00000000
R VCP_A_CFG_vcpemu 0x0000000B 0x00000000
R VCP_B_CFG_vcppid 0x0000000B 0x480A0000
R VCP_B_CFG_vcpexe 0x0000000B 0x00000000
R VCP_B_CFG_vcpend 0x0000000B 0x00000000
R VCP_B_CFG_vcpstat0 0x0000000B 0x00000010
R VCP_B_CFG_vcpstat1 0x0000000B 0x00000000
R VCP_B_CFG_vcperr 0x0000000B 0x00000000
R VCP_B_CFG_vcpemu 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Periperal_ID_Register 0x0000000B 0x48040122
R TCP3D_CFG_TCP3d_Mode_Control_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Endianess_Control_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Emulation_Control_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Execution_Control_Register_Process_0 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Execution_Control_Register_Process_1 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Status_Register_Process_0 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Status_Register_Process_1 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Event_Set_Register_Process_0 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Event_Set_Register_Process_1 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Raw_Status_and_Set 0x0000000B 0x02000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Raw_Status_and_Set 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Clear_Register_Process_0 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Clear_Register_Process_1 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enabled_Status_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enabled_Status_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enable_and_Set_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enable_and_Set_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Error_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_End_of_Interrupt_Register 0x0000000B 0x00000000
R TCP3D_CFG_TCP3d_Soft_Reset_Register 0x0000000B 0x00000000
R TIMER0_emumgt_clkspd 0x0000000B 0x00060000
R TIMER0_cntlo 0x0000000B 0x00000000
R TIMER0_cnthi 0x0000000B 0x00000000
R TIMER0_prdlo 0x0000000B 0x00000000
R TIMER0_prdhi 0x0000000B 0x00000000
R TIMER0_tcr 0x0000000B 0x00000000
R TIMER0_tgcr 0x0000000B 0x00000000
R TIMER0_wdtcr 0x0000000B 0x00000000
R TIMER1_emumgt_clkspd 0x0000000B 0x00060000
R TIMER1_cntlo 0x0000000B 0x00000000
R TIMER1_cnthi 0x0000000B 0x00000000
R TIMER1_prdlo 0x0000000B 0x00000000
R TIMER1_prdhi 0x0000000B 0x00000000
R TIMER1_tcr 0x0000000B 0x00000000
R TIMER1_tgcr 0x0000000B 0x00000000
R TIMER1_wdtcr 0x0000000B 0x00000000
R TIMER2_emumgt_clkspd 0x0000000B 0x00060000
R TIMER2_cntlo 0x0000000B 0x00000000
R TIMER2_cnthi 0x0000000B 0x00000000
R TIMER2_prdlo 0x0000000B 0x00000000
R TIMER2_prdhi 0x0000000B 0x00000000
R TIMER2_tcr 0x0000000B 0x00000000
R TIMER2_tgcr 0x0000000B 0x00000000
R TIMER2_wdtcr 0x0000000B 0x00000000
R TIMER3_emumgt_clkspd 0x0000000B 0x00060000
R TIMER3_cntlo 0x0000000B 0x00000000
R TIMER3_cnthi 0x0000000B 0x00000000
R TIMER3_prdlo 0x0000000B 0x00000000
R TIMER3_prdhi 0x0000000B 0x00000000
R TIMER3_tcr 0x0000000B 0x00000000
R TIMER3_tgcr 0x0000000B 0x00000000
R TIMER3_wdtcr 0x0000000B 0x00000000
R TIMER4_emumgt_clkspd 0x0000000B 0x00060000
R TIMER4_cntlo 0x0000000B 0x00000000
R TIMER4_cnthi 0x0000000B 0x00000000
R TIMER4_prdlo 0x0000000B 0x00000000
R TIMER4_prdhi 0x0000000B 0x00000000
R TIMER4_tcr 0x0000000B 0x00000000
R TIMER4_tgcr 0x0000000B 0x00000000
R TIMER4_wdtcr 0x0000000B 0x00000000
R TIMER5_emumgt_clkspd 0x0000000B 0x00060000
R TIMER5_cntlo 0x0000000B 0x00000000
R TIMER5_cnthi 0x0000000B 0x00000000
R TIMER5_prdlo 0x0000000B 0x00000000
R TIMER5_prdhi 0x0000000B 0x00000000
R TIMER5_tcr 0x0000000B 0x00000000
R TIMER5_tgcr 0x0000000B 0x00000000
R TIMER5_wdtcr 0x0000000B 0x00000000
R TIMER6_emumgt_clkspd 0x0000000B 0x00060000
R TIMER6_cntlo 0x0000000B 0x00000000
R TIMER6_cnthi 0x0000000B 0x00000000
R TIMER6_prdlo 0x0000000B 0x00000000
R TIMER6_prdhi 0x0000000B 0x00000000
R TIMER6_tcr 0x0000000B 0x00000000
R TIMER6_tgcr 0x0000000B 0x00000000
R TIMER6_wdtcr 0x0000000B 0x00000000
R TIMER7_emumgt_clkspd 0x0000000B 0x00060000
R TIMER7_cntlo 0x0000000B 0x00000000
R TIMER7_cnthi 0x0000000B 0x00000000
R TIMER7_prdlo 0x0000000B 0x00000000
R TIMER7_prdhi 0x0000000B 0x00000000
R TIMER7_tcr 0x0000000B 0x00000000
R TIMER7_tgcr 0x0000000B 0x00000000
R TIMER7_wdtcr 0x0000000B 0x00000000
R PLL_rstype 0x0000000B 0x00000001
R PLL_rstctrl 0x0000000B 0x00010003
R PLL_rstcfg 0x0000000B 0x00000000
R PLL_rsiso 0x0000000B 0x00000000
R PLL_pllctl 0x0000000B 0x00000041
R PLL_secctl 0x0000000B 0x00090000
R PLL_pllm 0x0000000B 0x0000001F
R PLL_prediv 0x0000000B 0x00000000
R PLL_plldiv1_3 0x0000000B 0x00008000
R PLL_postdiv 0x0000000B 0x00000000
R PLL_pllcmd 0x0000000B 0x00000001
R PLL_pllstat 0x0000000B 0x00000006
R PLL_alnctl 0x0000000B 0x00001FFF
R PLL_dchange 0x0000000B 0x00000000
R PLL_cken 0x0000000B 0x00000000
R PLL_ckstat 0x0000000B 0x00000000
R PLL_systat 0x0000000B 0x00001FFF
R PLL_plldiv4_16 0x0000000B 0x00008002
R GPIO_pid 0x0000000B 0x44831105
R GPIO_pcr 0x0000000B 0x00000001
R GPIO_binten 0x0000000B 0x00000000
R GPIO_bank_registers_dir 0x0000000B 0xFFFFFFFF
R GPIO_bank_registers_out_data 0x0000000B 0x00000000
R GPIO_bank_registers_set_data 0x0000000B 0x00000000
R GPIO_bank_registers_clr_data 0x0000000B 0x00000000
R GPIO_bank_registers_in_data 0x0000000B 0x00000501
R GPIO_bank_registers_set_ris_trig 0x0000000B 0x00000000
R GPIO_bank_registers_clr_ris_trig 0x0000000B 0x00000000
R GPIO_bank_registers_set_fal_trig 0x0000000B 0x00000000
R GPIO_bank_registers_clr_fal_trig 0x0000000B 0x00000000
R GPIO_bank_registers_intstat 0x0000000B 0x00000000
R PSC_pid 0x0000000B 0x44826200
R PSC_vcntlid 0x0000000B 0x0FFF0000
R PSC_ptcmd 0x0000000B 0x00000000
R PSC_ptstat 0x0000000B 0x00000000
R PSC_pdstat 0x0000000B 0x00000301
R PSC_pdctl 0x0000000B 0x00000001
R PSC_mdstat 0x0000000B 0x00001F03
R PSC_mdctl 0x0000000B 0x00000103
R MPU0_Revision_Register 0x0000000B 0x4E815101
R MPU0_Configuration_Register 0x0000000B 0x00000001
R MPU0_Interrupt_Raw_Status_Set_Register 0x0000000B 0x00000000
R MPU0_Interrupt_Enabled_Status_Clear_Register 0x0000000B 0x00000000
R MPU0_Interrupt_Enable_Register 0x0000000B 0x00000000
R MPU0_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R MPU0_EOI_Register 0x0000000B 0x00000000
R MPU0_Interrupt_Vector_Register 0x0000000B 0x00000000
R MPU0_Fixed_Start_Address_Register 0x0000000B 0x00000000
R MPU0_Fixed_End_Address_Register 0x0000000B 0x00000000
R MPU0_Fixed_MPPA_Register 0x0000000B 0x00000000
R MPU0_Programmable_Start_Address_Register 0x0000000B 0x01D00000
R MPU0_Programmable_End_Address_Register 0x0000000B 0x01D803FF
R MPU0_Programmable_MPPA_Register 0x0000000B 0x03FFFCB6
R MPU0_Fault_Address_Register 0x0000000B 0x00000000
R MPU0_Fault_Status_Register 0x0000000B 0x00000000
R MPU0_Fault_Clear_Register 0x0000000B 0x00000000
R MPU1_Revision_Register 0x0000000B 0x4E815101
R MPU1_Configuration_Register 0x0000000B 0x00050001
R MPU1_Interrupt_Raw_Status_Set_Register 0x0000000B 0x00000000
R MPU1_Interrupt_Enabled_Status_Clear_Register 0x0000000B 0x00000000
R MPU1_Interrupt_Enable_Register 0x0000000B 0x00000000
R MPU1_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R MPU1_EOI_Register 0x0000000B 0x00000000
R MPU1_Interrupt_Vector_Register 0x0000000B 0x00000000
R MPU1_Fixed_Start_Address_Register 0x0000000B 0x00000000
R MPU1_Fixed_End_Address_Register 0x0000000B 0x00000000
R MPU1_Fixed_MPPA_Register 0x0000000B 0x00000000
R MPU1_Programmable_Start_Address_Register 0x0000000B 0x34000000
R MPU1_Programmable_End_Address_Register 0x0000000B 0x3401FFFF
R MPU1_Programmable_MPPA_Register 0x0000000B 0x03FFFC80
R MPU1_Fault_Address_Register 0x0000000B 0x00000000
R MPU1_Fault_Status_Register 0x0000000B 0x00000000
R MPU1_Fault_Clear_Register 0x0000000B 0x00000000
R MPU2_Revision_Register 0x0000000B 0x4E815101
R MPU2_Configuration_Register 0x0000000B 0x00000001
R MPU2_Interrupt_Raw_Status_Set_Register 0x0000000B 0x00000000
R MPU2_Interrupt_Enabled_Status_Clear_Register 0x0000000B 0x00000000
R MPU2_Interrupt_Enable_Register 0x0000000B 0x00000000
R MPU2_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R MPU2_EOI_Register 0x0000000B 0x00000000
R MPU2_Interrupt_Vector_Register 0x0000000B 0x00000000
R MPU2_Fixed_Start_Address_Register 0x0000000B 0x00000000
R MPU2_Fixed_End_Address_Register 0x0000000B 0x00000000
R MPU2_Fixed_MPPA_Register 0x0000000B 0x00000000
R MPU2_Programmable_Start_Address_Register 0x0000000B 0x02A00000
R MPU2_Programmable_End_Address_Register 0x0000000B 0x02A1FFFF
R MPU2_Programmable_MPPA_Register 0x0000000B 0x03FFFCE4
R MPU2_Fault_Address_Register 0x0000000B 0x00000000
R MPU2_Fault_Status_Register 0x0000000B 0x00000000
R MPU2_Fault_Clear_Register 0x0000000B 0x00000000
R MPU3_Revision_Register 0x0000000B 0x4E815101
R MPU3_Configuration_Register 0x0000000B 0x00010001
R MPU3_Interrupt_Raw_Status_Set_Register 0x0000000B 0x00000000
R MPU3_Interrupt_Enabled_Status_Clear_Register 0x0000000B 0x00000000
R MPU3_Interrupt_Enable_Register 0x0000000B 0x00000000
R MPU3_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R MPU3_EOI_Register 0x0000000B 0x00000000
R MPU3_Interrupt_Vector_Register 0x0000000B 0x00000000
R MPU3_Fixed_Start_Address_Register 0x0000000B 0x00000000
R MPU3_Fixed_End_Address_Register 0x0000000B 0x00000000
R MPU3_Fixed_MPPA_Register 0x0000000B 0x00000000
R MPU3_Programmable_Start_Address_Register 0x0000000B 0x02640000
R MPU3_Programmable_End_Address_Register 0x0000000B 0x026407FF
R MPU3_Programmable_MPPA_Register 0x0000000B 0x0003FCB6
R MPU3_Fault_Address_Register 0x0000000B 0x00000000
R MPU3_Fault_Status_Register 0x0000000B 0x00000000
R MPU3_Fault_Clear_Register 0x0000000B 0x00000000
R MPU4_Revision_Register 0x0000000B 0x4E815101
R MPU4_Configuration_Register 0x0000000B 0x00000001
R MPU4_Interrupt_Raw_Status_Set_Register 0x0000000B 0x00000000
R MPU4_Interrupt_Enabled_Status_Clear_Register 0x0000000B 0x00000000
R MPU4_Interrupt_Enable_Register 0x0000000B 0x00000000
R MPU4_Interrupt_Enable_Clear_Register 0x0000000B 0x00000000
R MPU4_EOI_Register 0x0000000B 0x00000000
R MPU4_Interrupt_Vector_Register 0x0000000B 0x00000000
R MPU4_Fixed_Start_Address_Register 0x0000000B 0x00000000
R MPU4_Fixed_End_Address_Register 0x0000000B 0x00000000
R MPU4_Fixed_MPPA_Register 0x0000000B 0x00000000
R MPU4_Programmable_Start_Address_Register 0x0000000B 0x70000000
R MPU4_Programmable_End_Address_Register 0x0000000B 0x70FFFFFF
R MPU4_Programmable_MPPA_Register 0x0000000B 0x03FFFCFF
R MPU4_Fault_Address_Register 0x0000000B 0x00000000
R MPU4_Fault_Status_Register 0x0000000B 0x00000000
R MPU4_Fault_Clear_Register 0x0000000B 0x00000000
R I2C_icoar 0x0000000B 0x00000000
R I2C_icimr 0x0000000B 0x00000000
R I2C_icstr 0x0000000B 0x00000410
R I2C_icclkl 0x0000000B 0x00000000
R I2C_icclkh 0x0000000B 0x00000000
R I2C_iccnt 0x0000000B 0x00000000
R I2C_icdrr 0x0000000B 0x00000000
R I2C_icsar 0x0000000B 0x000003FF
R I2C_icdxr 0x0000000B 0x00000000
R I2C_icmdr 0x0000000B 0x00000000
R I2C_icivr 0x0000000B 0x00000000
R I2C_icemdr 0x0000000B 0x00000001
R I2C_icpsc 0x0000000B 0x00000000
R I2C_icpid1 0x0000000B 0x00004415
R I2C_icpid2 0x0000000B 0x00002206
R UART0_rbr 0x0000000B 0x00000000
R UART0_ier 0x0000000B 0x00000000
R UART0_iir 0x0000000B 0x00000001
R UART0_lcr 0x0000000B 0x00000000
R UART0_mcr 0x0000000B 0x00000000
R UART0_lsr 0x0000000B 0x00000060
R UART0_msr 0x0000000B 0x00000000
R UART0_scr 0x0000000B 0x00000000
R UART0_dll 0x0000000B 0x00000000
R UART0_dlh 0x0000000B 0x00000000
R UART0_revid1 0x0000000B 0x44141102
R UART0_revid2 0x0000000B 0x00000000
R UART0_pwremu_mgmt 0x0000000B 0x00000002
R UART0_mdr 0x0000000B 0x00000000
R UART1_rbr 0x0000000B 0x00000000
R UART1_ier 0x0000000B 0x00000000
R UART1_iir 0x0000000B 0x00000001
R UART1_lcr 0x0000000B 0x00000000
R UART1_mcr 0x0000000B 0x00000000
R UART1_lsr 0x0000000B 0x00000060
R UART1_msr 0x0000000B 0x00000010
R UART1_scr 0x0000000B 0x00000000
R UART1_dll 0x0000000B 0x00000000
R UART1_dlh 0x0000000B 0x00000000
R UART1_revid1 0x0000000B 0x44141102
R UART1_revid2 0x0000000B 0x00000000
R UART1_pwremu_mgmt 0x0000000B 0x00000002
R UART1_mdr 0x0000000B 0x00000000
R INTC0_revision_reg 0x0000000B 0x4E82A900
R INTC0_control_reg 0x0000000B 0x00000000
R INTC0_host_control_reg 0x0000000B 0x00000000
R INTC0_global_enable_hint_reg 0x0000000B 0x00000000
R INTC0_glb_nest_level_reg 0x0000000B 0x00000000
R INTC0_status_set_index_reg 0x0000000B 0x00000000
R INTC0_status_clr_index_reg 0x0000000B 0x00000000
R INTC0_enable_set_index_reg 0x0000000B 0x00000000
R INTC0_enable_clr_index_reg 0x0000000B 0x00000000
R INTC0_hint_enable_set_index_reg 0x0000000B 0x00000000
R INTC0_hint_enable_clr_index_reg 0x0000000B 0x00000000
R INTC0_vector_null_reg 0x0000000B 0x00000000
R INTC0_glb_pri_intr_reg 0x0000000B 0x00000000
R INTC0_glb_vector_addr_reg 0x0000000B 0x00000000
R INTC0_global_secure_enable_reg 0x0000000B 0x00000000
R INTC0_secure_pri_intr_reg 0x0000000B 0x00000000
R INTC0_raw_status_reg 0x0000000B 0x00000000
R INTC0_ena_status_reg 0x0000000B 0x00000000
R INTC0_enable_reg 0x0000000B 0x00000000
R INTC0_enable_clr_reg 0x0000000B 0x00000000
R INTC0_ch_map 0x0000000B 0x00000000
R INTC0_hint_map 0x0000000B 0x03020100
R INTC0_pri_hint_reg 0x0000000B 0x00000000
R INTC0_polarity_reg 0x0000000B 0x00000000
R INTC0_type_reg 0x0000000B 0x00000000
R INTC0_dbg_select_reg 0x0000000B 0x00000000
R INTC0_secure_enable_reg 0x0000000B 0x00000000
R INTC0_secure_enable_clr_reg 0x0000000B 0x00000000
R INTC0_nest_level_reg 0x0000000B 0x00000000
R INTC0_enable_hint_reg 0x0000000B 0x00000000
R INTC1_revision_reg 0x0000000B 0x4E82A900
R INTC1_control_reg 0x0000000B 0x00000000
R INTC1_host_control_reg 0x0000000B 0x00000000
R INTC1_global_enable_hint_reg 0x0000000B 0x00000000
R INTC1_glb_nest_level_reg 0x0000000B 0x00000000
R INTC1_status_set_index_reg 0x0000000B 0x00000000
R INTC1_status_clr_index_reg 0x0000000B 0x00000000
R INTC1_enable_set_index_reg 0x0000000B 0x00000000
R INTC1_enable_clr_index_reg 0x0000000B 0x00000000
R INTC1_hint_enable_set_index_reg 0x0000000B 0x00000000
R INTC1_hint_enable_clr_index_reg 0x0000000B 0x00000000
R INTC1_vector_null_reg 0x0000000B 0x00000000
R INTC1_glb_pri_intr_reg 0x0000000B 0x00000000
R INTC1_glb_vector_addr_reg 0x0000000B 0x00000000
R INTC1_global_secure_enable_reg 0x0000000B 0x00000000
R INTC1_secure_pri_intr_reg 0x0000000B 0x00000000
R INTC1_raw_status_reg 0x0000000B 0x00000000
R INTC1_ena_status_reg 0x0000000B 0x00000000
R INTC1_enable_reg 0x0000000B 0x00000000
R INTC1_enable_clr_reg 0x0000000B 0x00000000
R INTC1_ch_map 0x0000000B 0x00000000
R INTC1_hint_map 0x0000000B 0x03020100
R INTC1_pri_hint_reg 0x0000000B 0x00000000
R INTC1_polarity_reg 0x0000000B 0x00000000
R INTC1_type_reg 0x0000000B 0x00000000
R INTC1_dbg_select_reg 0x0000000B 0x00000000
R INTC1_secure_enable_reg 0x0000000B 0x00000000
R INTC1_secure_enable_clr_reg 0x0000000B 0x00000000
R INTC1_nest_level_reg 0x0000000B 0x00000000
R INTC1_enable_hint_reg 0x0000000B 0x00000000
R INTC2_revision_reg 0x0000000B 0x4E82A900
R INTC2_control_reg 0x0000000B 0x00000000
R INTC2_host_control_reg 0x0000000B 0x00000000
R INTC2_global_enable_hint_reg 0x0000000B 0x00000000
R INTC2_glb_nest_level_reg 0x0000000B 0x00000000
R INTC2_status_set_index_reg 0x0000000B 0x00000000
R INTC2_status_clr_index_reg 0x0000000B 0x00000000
R INTC2_enable_set_index_reg 0x0000000B 0x00000000
R INTC2_enable_clr_index_reg 0x0000000B 0x00000000
R INTC2_hint_enable_set_index_reg 0x0000000B 0x00000000
R INTC2_hint_enable_clr_index_reg 0x0000000B 0x00000000
R INTC2_vector_null_reg 0x0000000B 0x00000000
R INTC2_glb_pri_intr_reg 0x0000000B 0x00000000
R INTC2_glb_vector_addr_reg 0x0000000B 0x00000000
R INTC2_global_secure_enable_reg 0x0000000B 0x00000000
R INTC2_secure_pri_intr_reg 0x0000000B 0x00000000
R INTC2_raw_status_reg 0x0000000B 0x00000000
R INTC2_ena_status_reg 0x0000000B 0x00000000
R INTC2_enable_reg 0x0000000B 0x00000000
R INTC2_enable_clr_reg 0x0000000B 0x00000000
R INTC2_ch_map 0x0000000B 0x00000000
R INTC2_hint_map 0x0000000B 0x03020100
R INTC2_pri_hint_reg 0x0000000B 0x00000000
R INTC2_polarity_reg 0x0000000B 0x00000000
R INTC2_type_reg 0x0000000B 0x00000000
R INTC2_dbg_select_reg 0x0000000B 0x00000000
R INTC2_secure_enable_reg 0x0000000B 0x00000000
R INTC2_secure_enable_clr_reg 0x0000000B 0x00000000
R INTC2_nest_level_reg 0x0000000B 0x00000000
R INTC2_enable_hint_reg 0x0000000B 0x00000000
R IPC_nmigr 0x0000000B 0x00000000
R IPC_ipcgr 0x0000000B 0x00000000
R IPC_ipcgrh 0x0000000B 0x00000000
R IPC_ipcar 0x0000000B 0x00000000
R IPC_ipcarh 0x0000000B 0x00000000
R SEM_Semaphore_Peripheral_ID_Register 0x0000000B 0x48021200
R SEM_Semaphore_Scratch_Register 0x0000000B 0x00000000
R SEM_Semaphore_Reset_Run_status_Register 0x0000000B 0x00000001
R SEM_Semaphore_EOI_Register 0x0000000B 0x00000000
R SEM_Semaphore_Error_Register 0x0000000B 0x00000000
R SEM_Semaphore_Error_Clear_Register 0x0000000B 0x00000000
R SEM_Semaphore_Error_Set_Register 0x0000000B 0x00000000
R SEM_Semaphore_Direct_Register_0 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_1 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_2 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_3 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_4 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_5 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_6 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_7 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_8 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_9 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_10 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_11 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_12 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_13 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_14 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_15 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_16 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_17 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_18 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_19 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_20 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_21 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_22 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_23 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_24 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_25 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_26 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_27 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_28 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_29 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_30 0x0000000B 0x00000001
R SEM_Semaphore_Direct_Register_31 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_0 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_1 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_2 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_3 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_4 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_5 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_6 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_7 0x0000000B 0x00000001
R SEM_SSemaphore_Indirect_Register_8 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_9 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_10 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_11 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_12 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_13 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_14 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_15 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_16 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_17 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_18 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_19 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_20 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_21 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_22 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_23 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_24 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_25 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_26 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_27 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_28 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_29 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_30 0x0000000B 0x00000001
R SEM_Semaphore_Indirect_Register_31 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_0 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_1 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_2 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_3 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_4 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_5 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_6 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_7 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_8 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_9 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_10 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_11 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_12 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_13 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_14 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_15 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_16 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_17 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_18 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_19 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_20 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_21 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_22 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_23 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_24 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_25 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_26 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_27 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_28 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_29 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_30 0x0000000B 0x00000001
R SEM_Semaphore_Query_Register_31 0x0000000B 0x00000001
R SEM_Semaphore_Flag_Register0 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Register1 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Register2 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Register3 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Clear_Register0 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Clear_Register1 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Clear_Register2 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Clear_Register3 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Set_Register0 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Set_Register1 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Set_Register2 0x0000000B 0x00000000
R SEM_Semaphore_Flag_Set_Register3 0x0000000B 0x00000000
R EDMACC0_tpcc_pid 0x0000000B 0x4001AB00
R EDMACC0_tpcc_cfg 0x0000000B 0x03335445
R EDMACC0_tpcc_clkgdis 0x0000000B 0x00000000
R EDMACC0_tpcc_dchmap 0x0000000B 0x00000000
R EDMACC0_tpcc_qchmap 0x0000000B 0x00000000
R EDMACC0_tpcc_dmaqnum 0x0000000B 0x00000000
R EDMACC0_tpcc_qdmaqnum 0x0000000B 0x00000000
R EDMACC0_tpcc_quetcmap 0x0000000B 0x00003210
R EDMACC0_tpcc_quepri 0x0000000B 0x00000000
R EDMACC0_tpcc_emr 0x0000000B 0x00000000
R EDMACC0_tpcc_emrh 0x0000000B 0x00000000
R EDMACC0_tpcc_emcr 0x0000000B 0x00000000
R EDMACC0_tpcc_emcrh 0x0000000B 0x00000000
R EDMACC0_tpcc_qemr 0x0000000B 0x00000000
R EDMACC0_tpcc_qemcr 0x0000000B 0x00000000
R EDMACC0_tpcc_ccerr 0x0000000B 0x00000000
R EDMACC0_tpcc_ccerrclr 0x0000000B 0x00000000
R EDMACC0_tpcc_eeval 0x0000000B 0x00000000
R EDMACC0_tpcc_dra_drae 0x0000000B 0x00000000
R EDMACC0_tpcc_dra_draeh 0x0000000B 0x00000000
R EDMACC0_tpcc_qrae 0x0000000B 0x00000000
R EDMACC0_tpcc_qe 0x0000000B 0x000000E0
R EDMACC0_tpcc_qstat 0x0000000B 0x00000000
R EDMACC0_tpcc_qwmthra 0x0000000B 0x10101010
R EDMACC0_tpcc_qwmthrb 0x0000000B 0x00000000
R EDMACC0_tpcc_ccstat 0x0000000B 0x00000000
R EDMACC0_tpcc_aetctl 0x0000000B 0x00000000
R EDMACC0_tpcc_aetstat 0x0000000B 0x00000000
R EDMACC0_tpcc_aetcmd 0x0000000B 0x00000000
R EDMACC0_tpcc_mpfar 0x0000000B 0x00000000
R EDMACC0_tpcc_mpfsr 0x0000000B 0x00000000
R EDMACC0_tpcc_mpfcr 0x0000000B 0x00000000
R EDMACC0_tpcc_mppag 0x0000000B 0x0000FEF6
R EDMACC0_tpcc_mppa 0x0000000B 0x0000FEF6
R EDMACC0_tpcc_er 0x0000000B 0x00000000
R EDMACC0_tpcc_erh 0x0000000B 0x00000000
R EDMACC0_tpcc_ecr 0x0000000B 0x00000000
R EDMACC0_tpcc_ecrh 0x0000000B 0x00000000
R EDMACC0_tpcc_esr 0x0000000B 0x00000000
R EDMACC0_tpcc_esrh 0x0000000B 0x00000000
R EDMACC0_tpcc_cer 0x0000000B 0x00000000
R EDMACC0_tpcc_cerh 0x0000000B 0x00000000
R EDMACC0_tpcc_eer 0x0000000B 0x00000000
R EDMACC0_tpcc_eerh 0x0000000B 0x00000000
R EDMACC0_tpcc_eecr 0x0000000B 0x00000000
R EDMACC0_tpcc_eecrh 0x0000000B 0x00000000
R EDMACC0_tpcc_eesr 0x0000000B 0x00000000
R EDMACC0_tpcc_eesrh 0x0000000B 0x00000000
R EDMACC0_tpcc_ser 0x0000000B 0x00000000
R EDMACC0_tpcc_serh 0x0000000B 0x00000000
R EDMACC0_tpcc_secr 0x0000000B 0x00000000
R EDMACC0_tpcc_secrh 0x0000000B 0x00000000
R EDMACC0_tpcc_ier 0x0000000B 0x00000000
R EDMACC0_tpcc_ierh 0x0000000B 0x00000000
R EDMACC0_tpcc_iecr 0x0000000B 0x00000000
R EDMACC0_tpcc_iecrh 0x0000000B 0x00000000
R EDMACC0_tpcc_iesr 0x0000000B 0x00000000
R EDMACC0_tpcc_iesrh 0x0000000B 0x00000000
R EDMACC0_tpcc_ipr 0x0000000B 0x00000000
R EDMACC0_tpcc_iprh 0x0000000B 0x00000000
R EDMACC0_tpcc_icr 0x0000000B 0x00000000
R EDMACC0_tpcc_icrh 0x0000000B 0x00000000
R EDMACC0_tpcc_ieval 0x0000000B 0x00000000
R EDMACC0_tpcc_qer 0x0000000B 0x00000000
R EDMACC0_tpcc_qeer 0x0000000B 0x00000000
R EDMACC0_tpcc_qeecr 0x0000000B 0x00000000
R EDMACC0_tpcc_qeesr 0x0000000B 0x00000000
R EDMACC0_tpcc_qser 0x0000000B 0x00000000
R EDMACC0_tpcc_qsecr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_er 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_erh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ecr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ecrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_esr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_esrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_cer 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_cerh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eer 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eerh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eecr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eecrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eesr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_eesrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ser 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_serh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_secr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_secrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ier 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ierh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_iecr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_iecrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_iesr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_iesrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ipr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_iprh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_icr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_icrh 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_ieval 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qer 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qeer 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qeecr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qeesr 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qser 0x0000000B 0x00000000
R EDMACC0_shadow_tpcc_qsecr 0x0000000B 0x00000000
R EDMACC0_paramset_opt 0x0000000B 0x2EDD6ABC
R EDMACC0_paramset_src 0x0000000B 0xB055B323
R EDMACC0_paramset_a_b_cnt 0x0000000B 0xBE9B2D70
R EDMACC0_paramset_dst 0x0000000B 0xBCDE08DF
R EDMACC0_paramset_src_dst_bidx 0x0000000B 0x42812E26
R EDMACC0_paramset_link_bcntrld 0x0000000B 0x60024A2D
R EDMACC0_paramset_src_dst_cidx 0x0000000B 0x08D6401D
R EDMACC0_paramset_ccnt 0x0000000B 0x3426D7E0
R SRIO_rio_pid 0x0000000B 0x44AB2101
R SRIO_rio_pcr 0x0000000B 0x00000001
R SRIO_rio_per_set_cntl 0x0000000B 0x00053800
R SRIO_rio_per_set_cntl_1 0x0000000B 0x00000000
R SRIO_rio_gbl_en 0x0000000B 0x00000001
R SRIO_rio_gbl_en_stat 0x0000000B 0x000007FF
R SRIO_rio_blk_en 0x0000000B 0x00000001
R SRIO_rio_blk_en_stat 0x0000000B 0x00000001
R SRIO_rio_multiid_reg 0x0000000B 0x00FFFFFF
R SRIO_rio_pf_16b_cntl 0x0000000B 0xFFFFFFFF
R SRIO_rio_pf_8b_cntl 0x0000000B 0x0003FFFF
R SRIO_rio_doorbell_icsr 0x0000000B 0x00000000
R SRIO_rio_doorbell_iccr 0x0000000B 0x00000000
R SRIO_rio_lsu_icsr 0x0000000B 0x00000000
R SRIO_rio_lsu_iccr 0x0000000B 0x00000000
R SRIO_rio_err_rst_evnt_icsr 0x0000000B 0x00000000
R SRIO_rio_err_rst_evnt_iccr 0x0000000B 0x00000000
R SRIO_rio_amu_icsr 0x0000000B 0x00000000
R SRIO_rio_amu_iccr 0x0000000B 0x00000000
R SRIO_rio_doorbell_icrr1 0x0000000B 0x00000000
R SRIO_rio_doorbell_icrr2 0x0000000B 0x00000000
R SRIO_rio_lsu0_module_icrr 0x0000000B 0x00000000
R SRIO_rio_lsu1_module_icrr 0x0000000B 0x00000000
R SRIO_rio_err_rst_evnt_icrr 0x0000000B 0x00000000
R SRIO_rio_err_rst_evnt_icrr2 0x0000000B 0x00000000
R SRIO_rio_err_rst_evnt_icrr3 0x0000000B 0x00000000
R SRIO_rio_amu_icrr1 0x0000000B 0x00000000
R SRIO_rio_amu_icrr2 0x0000000B 0x00000000
R SRIO_rio_interrupt_ctl 0x0000000B 0x00000000
R SRIO_rio_intdst_decode 0x0000000B 0x00000000
R SRIO_rio_intdst_rate_cnt 0x0000000B 0x00000000
R SRIO_rio_intdst_rate_dis 0x0000000B 0x00000000
R SRIO_rio_rxu_map_l 0x0000000B 0xFF000000
R SRIO_rio_rxu_map_h 0x0000000B 0x00002000
R SRIO_rio_rxu_map_qid 0x0000000B 0x00000000
R SRIO_rio_rxu_type9_map0 0x0000000B 0x00000000
R SRIO_rio_rxu_type9_map1 0x0000000B 0x00002000
R SRIO_rio_rxu_type9_map2 0x0000000B 0xFFFF0000
R SRIO_rio_amu_srcid_map 0x0000000B 0x00000000
R SRIO_rio_amu_window_reg0 0x0000000B 0x10080000
R SRIO_rio_amu_window_reg1 0x0000000B 0x00000000
R SRIO_rio_amu_window_reg2 0x0000000B 0x00000000
R SRIO_rio_amu_priority_map 0x0000000B 0x00000000
R SRIO_rio_amu_capt0_map 0x0000000B 0x00000000
R SRIO_rio_amu_capt1_map 0x0000000B 0x00000000
R SRIO_rio_amu_window_pane 0x0000000B 0x00000000
R SRIO_rio_amu_flow_masks0 0x0000000B 0xFFFFFFFF
R SRIO_rio_lsu_reg0 0x0000000B 0x00000000
R SRIO_rio_lsu_reg1 0x0000000B 0x00000000
R SRIO_rio_lsu_reg2 0x0000000B 0x00000000
R SRIO_rio_lsu_reg3 0x0000000B 0x00000000
R SRIO_rio_lsu_reg4 0x0000000B 0x00000000
R SRIO_rio_lsu_reg5 0x0000000B 0x0000FF00
R SRIO_rio_lsu_reg6 0x0000000B 0x00000010
R SRIO_rio_lsu_setup_reg0 0x0000000B 0x44444444
R SRIO_rio_lsu_setup_reg1 0x0000000B 0x00000000
R SRIO_lsu_stat_reg 0x0000000B 0x00000000
R SRIO_rio_lsu_flow_masks 0x0000000B 0xFFFFFFFF
R SRIO_rio_supervisor_id 0x0000000B 0x00000000
R SRIO_rio_flow_cntl 0x0000000B 0x00010000
R SRIO_rio_tx_cppi_flow_masks 0x0000000B 0xFFFFFFFF
R SRIO_rio_tx_queue_sch_info 0x0000000B 0x06060606
R SRIO_rio_garbage_coll_qid0 0x0000000B 0x00000000
R SRIO_rio_garbage_coll_qid1 0x0000000B 0x00000000
R SRIO_rio_garbage_coll_qid2 0x0000000B 0x00000000
R SRIO_rio_dev_id 0x0000000B 0x00000000
R SRIO_rio_dev_info 0x0000000B 0x00000000
R SRIO_rio_asbly_id 0x0000000B 0x00000000
R SRIO_rio_asbly_info 0x0000000B 0x00000000
R SRIO_rio_pe_feat 0x0000000B 0x00000000
R SRIO_rio_sw_port 0x0000000B 0x00000000
R SRIO_rio_src_op 0x0000000B 0x00000000
R SRIO_rio_dest_op 0x0000000B 0x00000000
R SRIO_rio_ds_info 0x0000000B 0x00000000
R SRIO_rio_ds_ll_ctl 0x0000000B 0x00000000
R SRIO_rio_pe_ll_ctl 0x0000000B 0x00000000
R SRIO_rio_lcl_cfg_hbar 0x0000000B 0x00000000
R SRIO_rio_lcl_cfg_bar 0x0000000B 0x00000000
R SRIO_rio_base_id 0x0000000B 0x00000000
R SRIO_rio_host_base_id_lock 0x0000000B 0x00000000
R SRIO_rio_comp_tag 0x0000000B 0x00000000
R SRIO_rio_sp_mb_head 0x0000000B 0x00000000
R SRIO_rio_sp_lt_ctl 0x0000000B 0x00000000
R SRIO_rio_sp_rt_ctl 0x0000000B 0x00000000
R SRIO_rio_sp_gen_ctl 0x0000000B 0x00000000
R SRIO_rio_sp_lm_req 0x0000000B 0x00000000
R SRIO_rio_sp_lm_resp 0x0000000B 0x00000000
R SRIO_rio_sp_ackid_stat 0x0000000B 0x00000000
R SRIO_rio_sp_ctl2 0x0000000B 0x00000000
R SRIO_rio_sp_err_stat 0x0000000B 0x00000000
R SRIO_rio_sp_ctl 0x0000000B 0x00000000
R SRIO_rio_err_rpt_bh 0x0000000B 0x00000000
R SRIO_rio_err_det 0x0000000B 0x00000000
R SRIO_rio_err_en 0x0000000B 0x00000000
R SRIO_rio_h_addr_capt 0x0000000B 0x00000000
R SRIO_rio_addr_capt 0x0000000B 0x00000000
R SRIO_rio_id_capt 0x0000000B 0x00000000
R SRIO_rio_ctrl_capt 0x0000000B 0x00000000
R SRIO_rio_pw_tgt_id 0x0000000B 0x00000000
R SRIO_rio_sp_err_det 0x0000000B 0x00000000
R SRIO_rio_sp_rate_en 0x0000000B 0x00000000
R SRIO_rio_sp_err_attr_capt 0x0000000B 0x00000000
R SRIO_rio_sp_err_capt_0 0x0000000B 0x00000000
R SRIO_rio_sp_err_capt_1 0x0000000B 0x00000000
R SRIO_rio_sp_err_capt_2 0x0000000B 0x00000000
R SRIO_rio_sp_err_capt_3 0x0000000B 0x00000000
R SRIO_rio_sp_err_rate 0x0000000B 0x00000000
R SRIO_rio_sp_err_thresh 0x0000000B 0x00000000
R SRIO_rio_per_lane_bh 0x0000000B 0x00000000
R SRIO_rio_lane_stat0 0x0000000B 0x00000000
R SRIO_rio_lane_stat1 0x0000000B 0x00000000
R SRIO_rio_plm_bh 0x0000000B 0x00000000
R SRIO_rio_plm_sp_imp_spec_ctl 0x0000000B 0x00000000
R SRIO_rio_plm_sp_pwdn_ctl 0x0000000B 0x00000000
R SRIO_rio_plm_sp_status 0x0000000B 0x00000000
R SRIO_rio_plm_sp_int_enable 0x0000000B 0x00000000
R SRIO_rio_plm_sp_pw_enable 0x0000000B 0x00000000
R SRIO_rio_plm_sp_event_gen 0x0000000B 0x00000000
R SRIO_rio_plm_sp_all_int_en 0x0000000B 0x00000000
R SRIO_rio_plm_sp_all_pw_en 0x0000000B 0x00000000
R SRIO_rio_plm_sp_path_ctl 0x0000000B 0x00000000
R SRIO_rio_plm_sp_discovery_timer 0x0000000B 0x00000000
R SRIO_rio_plm_sp_silence_timer 0x0000000B 0x00000000
R SRIO_rio_plm_sp_vmin_exp 0x0000000B 0x00000000
R SRIO_rio_plm_sp_pol_ctl 0x0000000B 0x00000000
R SRIO_rio_plm_sp_denial_ctl 0x0000000B 0x00000000
R SRIO_rio_plm_sp_rcvd_mecs 0x0000000B 0x00000000
R SRIO_rio_plm_sp_mecs_fwd 0x0000000B 0x00000000
R SRIO_rio_plm_sp_long_cs_tx1 0x0000000B 0x00000000
R SRIO_rio_plm_sp_long_cs_tx2 0x0000000B 0x00000000
R SRIO_rio_tlm_bh 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_control 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_status 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_int_enable 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_pw_enable 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_event_gen 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_0_ctl 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_0_pattern_match 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_1_ctl 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_1_pattern_match 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_2_ctl 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_2_pattern_match 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_3_ctl 0x0000000B 0x00000000
R SRIO_rio_tlm_sp_brr_3_pattern_match 0x0000000B 0x00000000
R SRIO_rio_pbm_bh 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_control 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_status 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_int_enable 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_pw_enable 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_event_gen 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_ig_resources 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_eg_resources 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_ig_watermark0 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_ig_watermark1 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_ig_watermark2 0x0000000B 0x00000000
R SRIO_rio_pbm_sp_ig_watermark3 0x0000000B 0x00000000
R SRIO_rio_em_bh 0x0000000B 0x00000000
R SRIO_rio_em_int_stat 0x0000000B 0x00000000
R SRIO_rio_em_int_enable 0x0000000B 0x00000000
R SRIO_rio_em_int_port_stat 0x0000000B 0x00000000
R SRIO_rio_em_pw_stat 0x0000000B 0x00000000
R SRIO_rio_em_pw_en 0x0000000B 0x00000000
R SRIO_rio_em_pw_port_stat 0x0000000B 0x00000000
R SRIO_rio_em_dev_int_en 0x0000000B 0x00000000
R SRIO_rio_em_dev_pw_en 0x0000000B 0x00000000
R SRIO_rio_em_mecs_stat 0x0000000B 0x00000000
R SRIO_rio_em_mecs_int_en 0x0000000B 0x00000000
R SRIO_rio_em_mecs_cap_en 0x0000000B 0x00000000
R SRIO_rio_em_mecs_trig_en 0x0000000B 0x00000000
R SRIO_rio_em_mecs_req 0x0000000B 0x00000000
R SRIO_rio_em_mecs_port_stat 0x0000000B 0x00000000
R SRIO_rio_em_mecs_event_gen 0x0000000B 0x00000000
R SRIO_rio_em_rst_port_stat 0x0000000B 0x00000000
R SRIO_rio_em_rst_int_en 0x0000000B 0x00000000
R SRIO_rio_em_rst_pw_en 0x0000000B 0x00000000
R SRIO_rio_pw_bh 0x0000000B 0x00000000
R SRIO_rio_pw_ctl 0x0000000B 0x00000000
R SRIO_rio_pw_route 0x0000000B 0x00000000
R SRIO_rio_pw_rx_stat 0x0000000B 0x00000000
R SRIO_rio_pw_rx_event_gen 0x0000000B 0x00000000
R SRIO_rio_pw_rx_capt 0x0000000B 0x00000000
R SRIO_rio_llm_bh 0x0000000B 0x00000000
R SRIO_rio_whiteboard 0x0000000B 0x00000000
R SRIO_rio_port_number 0x0000000B 0x00000000
R SRIO_rio_prescalar_srv_clk 0x0000000B 0x00000000
R SRIO_rio_reg_rst_ctl 0x0000000B 0x00000000
R SRIO_rio_local_err_det 0x0000000B 0x00000000
R SRIO_rio_local_err_en 0x0000000B 0x00000000
R SRIO_rio_local_h_addr_capt 0x0000000B 0x00000000
R SRIO_rio_local_addr_capt 0x0000000B 0x00000000
R SRIO_rio_local_id_capt 0x0000000B 0x00000000
R SRIO_rio_local_ctrl_capt 0x0000000B 0x00000000
R SRIO_rio_fabric_bh 0x0000000B 0x00000000
R SRIO_rio_fabric_csr 0x0000000B 0x00000000
R SRIO_rio_sp_fabric_status 0x0000000B 0x00000000
R SRIO_PKTDMA_CTRL_Revision_Register 0x0000000B 0x4E5AC900
R SRIO_PKTDMA_CTRL_Performance_Control_Register 0x0000000B 0x00200000
R SRIO_PKTDMA_CTRL_Emulation_Control_Register 0x0000000B 0x80000000
R SRIO_PKTDMA_CTRL_Priority_Control_Register 0x0000000B 0x00000000
R SRIO_PKTDMA_CTRL_Queue_Manager_0_Base_Address_Register 0x0000000B 0x34020000
R SRIO_PKTDMA_CTRL_Queue_Manager_1_Base_Address_Register 0x0000000B 0x00000000
R SRIO_PKTDMA_CTRL_Queue_Manager_2_Base_Address_Register 0x0000000B 0x00000000
R SRIO_PKTDMA_CTRL_Queue_Manager_3_Base_Address_Register 0x0000000B 0x00000000
R SRIO_PKTDMA_TX_CHANNEL_Global_Config_Register_A 0x0000000B 0x00000000
R SRIO_PKTDMA_TX_CHANNEL_Global_Config_Register_B 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_CHANNEL_Global_Config_Register_A 0x0000000B 0x00000000
R SRIO_PKTDMA_TX_SCHED_Scheduler_Config_Register 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_A 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_B 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_C 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_D 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_E 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_F 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_G 0x0000000B 0x00000000
R SRIO_PKTDMA_RX_FLOW_Config_Register_H 0x0000000B 0x00000000
R QMSS_REVISION_REG 0x0000000B 0x4E530800
R QMSS_QUEUE_DIVERSION_REG 0x0000000B 0x00000000
R QMSS_LINKING_RAM_REGION_0_BASE_ADDRESS_REG 0x0000000B 0x00000000
R QMSS_LINKING_RAM_REGION_0_SIZE_REG 0x0000000B 0x00000000
R QMSS_LINKING_RAM_REGION_1_BASE_ADDRESS_REG 0x0000000B 0x00000000
R QMSS_FREE_DESCRIPTOR_STARVE_COUNT_REG 0x0000000B 0x00000000
R QMSS_MEMORY_REGION_BASE_ADDRESS_REG 0x0000000B 0x00000000
R QMSS_MEMORY_REGION_START_INDEX_REG 0x0000000B 0x00000000
R QMSS_MEMORY_REGION_DESCRIPTOR_SETUP_REG 0x0000000B 0x00000000
R QMSS_QUEUE_STATUS_CONFIG_REG_A 0x0000000B 0x00000000
R QMSS_QUEUE_STATUS_CONFIG_REG_B 0x0000000B 0x00000000
R QMSS_QUEUE_STATUS_CONFIG_REG_C 0x0000000B 0x00000000
R QMSS_QUEUE_STATUS_CONFIG_REG_D 0x0000000B 0x00000081
R QMSS_INTD_REVISION 0x0000000B 0x4E83B100
R QMSS_INTD_EOI 0x0000000B 0x00000000
R QMSS_INTD_STATUS0 0x0000000B 0x00000000
R QMSS_INTD_STATUS1 0x0000000B 0x00000000
R QMSS_INTD_STATUS4 0x0000000B 0x00000000
R QMSS_INTD_STATUS_CLR0 0x0000000B 0x00000000
R QMSS_INTD_STATUS_CLR1 0x0000000B 0x00000000
R QMSS_INTD_STATUS_CLR4 0x0000000B 0x00000000
R QMSS_INTD_INTCNT 0x0000000B 0x00000000
R QMSS_PDSP_CMD_INTERFACE_PDSP_CONTROL 0x0000000B 0xE9504E5D
R QMSS_PDSP_CMD_INTERFACE_PDSP_STATUS 0x0000000B 0xFEA2FBFE
R QMSS_PDSP_CMD_INTERFACE_PDSP_WAKEUP_ENABLE 0x0000000B 0xC335C188
R QMSS_PDSP_CMD_INTERFACE_PDSP_CYCLE_COUNT 0x0000000B 0x9D6C3D4C
R QMSS_PDSP_CMD_INTERFACE_PDSP_STALL_COUNT 0x0000000B 0x7D0B7400
R QMSS_PDSP_CMD_INTERFACE_PDSP_CONSTANT_TABLE_BLOCK_INDEX_0 0x0000000B 0x614CABCD
R QMSS_PDSP_CMD_INTERFACE_PDSP_CONSTANT_TABLE_BLOCK_INDEX_1 0x0000000B 0x94EDA21C
R QMSS_PDSP_CMD_INTERFACE_PDSP_CONSTANT_TABLE_PROG_PTR_0 0x0000000B 0x138A0C23
R QMSS_PDSP_CMD_INTERFACE_PDSP_CONSTANT_TABLE_PROG_PTR_1 0x0000000B 0xBB6FC61A
R QMSS_PDSP_CMD_INTERFACE_PDSP_RAM 0x0000000B 0x00000000
R QMSS_PKTDMA_CTRL_Revision_Register 0x0000000B 0x4E5AB100
R QMSS_PKTDMA_CTRL_Performance_Control_Register 0x0000000B 0x00200000
R QMSS_PKTDMA_CTRL_Emulation_Control_Register 0x0000000B 0x80000000
R QMSS_PKTDMA_CTRL_Priority_Control_Register 0x0000000B 0x00000000
R QMSS_PKTDMA_CTRL_Queue_Manager_0_Base_Address_Register 0x0000000B 0x34020000
R QMSS_PKTDMA_CTRL_Queue_Manager_1_Base_Address_Register 0x0000000B 0x34020000
R QMSS_PKTDMA_CTRL_Queue_Manager_2_Base_Address_Register 0x0000000B 0x00000000
R QMSS_PKTDMA_CTRL_Queue_Manager_3_Base_Address_Register 0x0000000B 0x00000000
R QMSS_PKTDMA_TX_CHANNEL_Global_Config_Register_A 0x0000000B 0x00000000
R QMSS_PKTDMA_TX_CHANNEL_Global_Config_Register_B 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_CHANNEL_Global_Config_Register_A 0x0000000B 0x00000000
R QMSS_PKTDMA_TX_SCHED_Scheduler_Config_Register 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_A 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_B 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_C 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_D 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_E 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_F 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_G 0x0000000B 0x00000000
R QMSS_PKTDMA_RX_FLOW_Config_Register_H 0x0000000B 0x00000000
R XMC_xmpax_xmpaxl 0x0000000B 0x000000BF
R XMC_xmpax_xmpaxh 0x0000000B 0x0000001E
R XMC_xmpfar 0x0000000B 0x00000000
R XMC_xmpfsr 0x0000000B 0x00000000
R XMC_xmpfcr 0x0000000B 0x00000000
R XMC_mdmaarbx 0x0000000B 0x00070000
R XMC_xpfcmd 0x0000000B 0x00000000
R XMC_xpfacs 0x0000000B 0x00000000
R XMC_xpfac0 0x0000000B 0x00000000
R XMC_xpfac1 0x0000000B 0x00000000
R XMC_xpfac2 0x0000000B 0x00000000
R XMC_xpfac3 0x0000000B 0x00000000
R XMC_xpfaddr 0x0000000B 0x00000000
R MSMC_pid 0x0000000B 0x45000000
R MSMC_smcc 0x0000000B 0x00000000
R MSMC_smcerrar 0x0000000B 0x00000000
R MSMC_smcerrxr 0x0000000B 0x00000000
R MSMC_smedcc 0x0000000B 0x44000001
R MSMC_smcea 0x0000000B 0x00000000
R MSMC_smsecc 0x0000000B 0x00000000
R MSMC_smpfar 0x0000000B 0x00000000
R MSMC_smpfxr 0x0000000B 0x00000000
R MSMC_smpfr 0x0000000B 0x00000000
R MSMC_smpfcr 0x0000000B 0x00000000
R MSMC_smsta 0x0000000B 0x80000000
R MSMC_sbnd 0x0000000B 0x001F001F
R MSMC_sbndm 0x0000000B 0x0000001F
R MSMC_sbnde 0x0000000B 0x001F001F
R MSMC_smedctst 0x0000000B 0x2C000000
R MSMC_cfglck 0x0000000B 0x00000000
R MSMC_cfgulck 0x0000000B 0x00000000
R MSMC_cfglckstat 0x0000000B 0x00000000
R MSMC_sms_mpax_lck 0x0000000B 0x00000000
R MSMC_sms_mpax_ulck 0x0000000B 0x00000000
R MSMC_sms_mpax_lckstat 0x0000000B 0x00000000
R MSMC_ses_mpax_lck 0x0000000B 0x00000000
R MSMC_ses_mpax_ulck 0x0000000B 0x00000000
R MSMC_ses_mpax_lckstat 0x0000000B 0x00000000
R MSMC_smestat 0x0000000B 0x00000000
R MSMC_smirstat 0x0000000B 0x00000000
R MSMC_smirc 0x0000000B 0x00000000
R MSMC_smiestat 0x0000000B 0x00000000
R MSMC_smiec 0x0000000B 0x00000000
R MSMC_smath 0x0000000B 0x00000000
R MSMC_smah 0x0000000B 0x00000000
R MSMC_smarm 0x0000000B 0x00000000
R MSMC_smawm 0x0000000B 0x00000000
R MSMC_smav 0x0000000B 0x00000000
R MSMC_smamp 0x0000000B 0x00000000
R MSMC_smaep 0x0000000B 0x00000000
R MSMC_smac 0x0000000B 0xFFFFFF1C
R MSMC_smcfg 0x0000000B 0x000001C0
R MSMC_smncerrar 0x0000000B 0x00000000
R MSMC_smncerrxr 0x0000000B 0x00000000
R MSMC_smncea 0x0000000B 0x00000000
R MSMC_sms_mpax_per_privid_sms_mpaxl 0x0000000B 0x00C000FF
R MSMC_sms_mpax_per_privid_sms_mpaxh 0x0000000B 0x0C000013
R MSMC_ses_mpax_per_privid_ses_mpaxl 0x0000000B 0x800000BF
R MSMC_ses_mpax_per_privid_ses_mpaxh 0x0000000B 0x8000001E
R TCP3D_DMA_TCP3d_Input_Configuration_Register_0_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_0_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_1_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_1_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_2_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_2_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_3_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_3_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_4_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_4_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_5_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_5_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_6_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_6_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_7_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_7_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_8_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_8_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_9_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_9_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_10_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_10_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_11_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_11_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_12_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_12_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_13_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_13_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_14_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Input_Configuration_Register_14_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Trigger_Control_Register_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Trigger_Control_Register_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_0_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_0_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_1_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_1_Process_1 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_2_Process_0 0x0000000B 0x00000000
R TCP3D_DMA_TCP3d_Output_Status_Register_2_Process_1 0x0000000B 0x00000000
R VCP_A_DATA_vcpic0 0x0000000B 0x00000000
R VCP_A_DATA_vcpic1 0x0000000B 0x00000000
R VCP_A_DATA_vcpic2 0x0000000B 0x00000000
R VCP_A_DATA_vcpic3 0x0000000B 0x00000000
R VCP_A_DATA_vcpic4 0x0000000B 0x00000000
R VCP_A_DATA_vcpic5 0x0000000B 0x00000000
R VCP_A_DATA_vcpout0 0x0000000B 0x00000000
R VCP_A_DATA_vcpout1 0x0000000B 0x00000000
R VCP_A_DATA_vcpwbm 0x0000000B 0x00000000
R VCP_A_DATA_vcprdecs 0x0000000B 0x1FD6C0CB
R VCP_B_DATA_vcpic0 0x0000000B 0x00000000
R VCP_B_DATA_vcpic1 0x0000000B 0x00000000
R VCP_B_DATA_vcpic2 0x0000000B 0x00000000
R VCP_B_DATA_vcpic3 0x0000000B 0x00000000
R VCP_B_DATA_vcpic4 0x0000000B 0x00000000
R VCP_B_DATA_vcpic5 0x0000000B 0x00000000
R VCP_B_DATA_vcpout0 0x0000000B 0x00000000
R VCP_B_DATA_vcpout1 0x0000000B 0x00000000
R VCP_B_DATA_vcpwbm 0x0000000B 0x00000000
R VCP_B_DATA_vcprdecs 0x0000000B 0x7C1EF663

8. Flash the app.dat file

Had Issues,  Loaded the app.dat file using my modified norwirter (only thing different is addition of print statements).  File loaded to Addr 0x80000000 Length 0xf0000.

...

Thanks,

Brad