AM4372: About Power-Down Sequencing

user1201164

Part Number: AM4372

Hi,

I have a question from one of our clients.
They are designing a custom board using AM4372, but have a question on Power-Down Sequencing.
In the dataSheet "5.12.1.3 Power-Down Sequencing" there is a description of 4 sequences.
The second one "If it is desired to ramp down VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] simultaneously,..." and the last one "When using simplified power-down sequence,...".
The simplified power-down sequence says that there is no order of down between each power supply. I understand from past questions and answers that this is simultaneous power-down.
However, I think this is the same in the second sequence, but here there is a condition attached. What is the difference?
If PWRONRSTn is asserted, is it OK to power down in the simplified sequence?

Best Regards,

Kouji Nishigata

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 192199 points

Hello Kouji Nishigata,

Thank you for the query.

Could you please help me understand the Power-Up Sequencing that you are considering to follow.

The Power-Down Sequencing definition is relative to the above.

Regards,

Sreenivasa

0 user1201164 over 3 years ago in reply to Kallikuppa Sreenivasa

Expert 1770 points

Hi, Sreenivasa

Thanks for the response.
I understand that both the simple power down sequence and the second one are SIMULTANEOUS POWER DOWN.
For The simplified power-down sequence, it says "there are no power-down requirements between the VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] supplies and are ramped down together without any reliability concerns".
However, in the second, "it should always be ensured that the difference between VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] during the entire power-down sequence is <2 V A" condition.

In the customer's design, the power-down sequence is almost simultaneous power down, but in the same order as the Power-Up Sequencing. They have not specifically included a condition like <2 V A at this time.
If this is The simplified power-down sequence, then there should be no problem, but if it corresponds to the second sequence, then you need to be careful. Where can we tell the difference?

Best Regards,

Kouji Nishigata

0 Kallikuppa Sreenivasa over 3 years ago in reply to user1201164

TI__Guru**** 192199 points

Hello Kouji Nishigata

Thank you for the inputs.

Let me review and comeback. Is this a discrete power solution that customer is using or a PMIC ?

Regards,

Sreenivasa

0 user1201164 over 3 years ago in reply to Kallikuppa Sreenivasa

Expert 1770 points

Hi, Sreenivasa

Thanks for the response.
The customer is considering the following configuration

Start-up: 3.3V⇒1.8V⇒1.5V⇒1.1V
Falling: 3.3V⇒1.8V⇒1.5V,1.1V

Best Regards,

Kouji Nishigata

0 Kallikuppa Sreenivasa over 3 years ago in reply to user1201164

TI__Guru**** 192199 points

Hello Kouji Nishigata,

Thank you for the inputs.

Does customer have a board designed ?

Not sure if this is a question for DC/DC converter team.

Regards,

Sreenivasa

0 user1201164 over 3 years ago in reply to Kallikuppa Sreenivasa

Expert 1770 points

Hi, Sreenivasa

Thanks for the response.
Yes, the customer is designing a custom board.

Best Regards,

Kouji Nishigata

0 Kallikuppa Sreenivasa over 3 years ago in reply to user1201164

TI__Guru**** 192199 points

Hello Kouji Nishigata,

Let me review and update you.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192199 points

Hello Kouji Nishigata,

Please refer below inputs received internally from the expert

The definition of Simplified Power Sequence is when the customer is using a single 3.3V power supply to source all AM437x 3.3V IO power rails (VDDSHVx) and they use the same 3.3V power supply to source our internal LDO (VDDS3P3V_IOLDO) that powers the IO bias power rails (VDDS and VDDS_CLKOUT) by connecting them to CAP_VDDS1P8V_IOLDO.

For this use case, we know our internal LDO will never allow the voltage difference between the IO supply (VDDSHVx) and the IO bias supply (VDDS and VDDS_CLKOUT) to exceed 2V. So we do not mention the requirement in this power-down option.

The third paragraph is describing a use case where they are supply the IO bias power rails (VDDS and VDDS_CLKOUT) from a power source other then the internal LDO. In this case they are responsible to ensure the voltage difference between the IO supply (VDDSHVx) and the IO bias supply (VDDS and VDDS_CLKOUT) never exceed 2V. So we mention the requirement in this power-down option.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192199 points

Hello Kouji Nishigata,

FYI, Just in case you have not had a chance to refer to the below thread.

(10) AM4372: power up/down sequence - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa