DRA829V: DDR initialization not completing with XDS110 connection to XDRA829VXXGALF

Hi Saravanakumar,

Have you validated this DDR with any test?

Also, can you please mention what is running on your board?

Regards,
Parth

Hi Parth,

We have checked in UART mode and No-boot mode. In both the modes, it is hanging like in the above attached imaged. We have validated this board last year. At that time, it worked and we can able to load the binary MCU_R5_0 core and ran the DDR stress test. We haven't used the board for months. Now we want to run the same DDR stress test in this board. But DDR initialization is not completing with the loadJSFile ("/home/bh/ti-processor-sdk-rtos-j721e-evm-07_03_00_07/psdkqa/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js") in CCS. I tried different working U-boot images but above issue repeating. Or is there any way to run the DDR Read/Write test?

Regards

Saravanakumar

Hi Saravanakumar,

Are you running a Linux + RTOS use case?
If you are running U-boot on A72, then you should not use launch.js script. What exactly is your use case and what are you trying to load?

Regards,
Parth

Hi Parth,

I will check and update. One more thing I want to know, we have old ccxml file already with us which configured with gel. That was worked when we are checking last year. Now the same ccxml file not working. I tried to configure new ccxml file as per the steps in https://software-dl.ti.com/jacinto7/esd/processor-sdk-qnx-jacinto7/07_02_00_04/exports/docs/ccs_setup_j721e.html. But we are not able to find the J721E.gel file in the folder path mentioned. Whether this gel file will work for out custom board, since we are using IS46LQ32256EA-062B2LA3 (ISSI part) in our board. We are trying to load board_diag_mem_mcu1_0_debug.xer5f file MCU_Cortex_R5_0 core.

Regards

Saravanakumar

Our intention is we want to run the DDR test (stress test or margin analysis like that). Please tell us the procedure to perform this in out custom board with XDRA829VXXGALF processor and IS46LQ32256EA-062B2LA3.

Hi Parth,

Any update on the above query.

Regards

Saravanakumar

Hi,

Saravanakumar Balasubramanian said:

I tried to configure new ccxml file as per the steps in https://software-dl.ti.com/jacinto7/esd/processor-sdk-qnx-jacinto7/07_02_00_04/exports/docs/ccs_setup_j721e.html.

The default GEL file will not work in your case. The GEL file needs to be configured as per the new DDR. I am notifying our DDR experts here, they can help you out with the required GEL configuration.

Regards,
Parth

Hi Parth,

I created new ccxml file with the GEL file shared by TI for our board as per the steps in software-dl.ti.com/.../ccs_setup_j721e.html . When launching the ccxml file  and loading the launch.js, it gives an error. Below is the error snapshot.

/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_j721e_2D00_ddr_2D00_evm_2D00_lp4_2D00_3200_5F00_exp1a.gel