TDA4VM: How to config DSS for BT601 output format in vision apps?

Hi henry wu,

henry wu said:

1. hFronPorch , hBackPorch and vSyncWidth are always 0 whenever I set them in above cells, it's normal?

Yes, that's normal, because for embedded sync output, it just has total blanking included in hsyncleng, there is no front/back porch. 

henry wu said:

2. Below is my setting, the value of width and height should I set in CSI capture module?

Did not get it. CSI capture does not need to include these timings.. 

The timings are for DSS output, where you want to get BT601 output. 

Regards,

Brijesh

Below is our data path. I mean what the value of width and height should I set in TDA4VM EVM board(Capture Board).

Width and Height will be same as what you are configuring in the VP, which outputs discrete sync...

Hi Brijesh,

I set capture size to 1856*750 in capture board and get below data.

(UYVY, 16bit packed)

Could you give some suggestions?

Thanks

PS: enable color bar output in send-board.

Can you please share the output image for analysis? 

Regards,

Brijesh

csix_raw_output_1856x750_ch_0_00001226.zip

Except the few initial lines, where only blanking data is available, the captured frame does not look correct. it looks like pixel values are repeated for almost 240 times. Is it what you are sending from DSS?

The 240 line almost equal  "hFrontPorch + hBackPorch + hSyncWidth + vFrontPorch + vBackPorch + vSyncWidth"

These blank value should set to 0？

Please check hsyncwidth and width. they are increased, because frontporch and backporch are included in them.

The similar is case on vertical size.. 

Regards,

Brijesh

Hi Brijesh,

The picture got from capture-board, it seems contain blank timing.

When I set blank timing to 0 like below:

And I got the picture， it also contains blank timing？It's normal? any suggestions?

Thankscsix_raw_output_1856x750_ch_0_00000042.zip

Hi henry wu,

Yes, blanking in embedded sync output in this case can be 0 in the parameters. This is perfectly fine. This is done to match timing with discrete sync output. 

You could now use either ACT VID signal or HSYNC signal from the other VP to get the sync signals and data from the embedded sync output. 

Regards,

Brijesh