McBSP-Digital loop back mode issue

Poornima Tom

I have configured McBSP0 in DLB mode.McBSP internal clock is used to generate CLKR/X & FSR/X. Also,FSGM=1 & FPER =32 bit frame & FWID =1.In the code i have tried to send 4 data words using DLB mode.But ,the problem is i'm recieving 1st data correctly . But from 2nd data onwards, i'm recieving different data.Please suggest on this issue.

void transfer(McBSP_reg *McBSP,unsigned int *source,unsigned int * dest)

{while(!(McBSP->SPCR & (0x1<<17))); //wait until XRDY =1

McBSP->DXR=*source;

printf("transmitted value:\t%02X\n",McBSP->DXR);

if(McBSP->SRGR&(0X1<<28)) //if FSGM=1

if(McBSP->SPCR&(0x1<<18))

McBSP->SPCR |=0x1<<23; //FRST=1

while(!(McBSP->SPCR&0x2)) ; //until RRDY=1

*dest=McBSP->DRR;

printf("recieved value:\t%02X\n",*dest);

}

void main()

{unsigned int data[4],Rxdata,i;

data[0]=5;

data[1]=2;

data[2]=3;

data[3]=6;

Rxdata=0;

PLLC0_init();

PLLC1_init();

PSC1_LPSC_Enable(0,14);

PINMUX1=0x22222220;

PINMUX2=0x02222220;

McBSP_init(McBSP0);

for(i=0;i<4;i++)

transfer(McBSP0,&data[i],&Rxdata);

}

void McBSP_init(McBSP_reg *McBSP)

{McBSP->SPCR &=~(0x00C000000);

while(McBSP->SPCR&0x00C000000);

McBSP->SPCR &=~(0x00010001);

McBSP->SRGR |=(0x1<<28) |0x2 ; //FSGM=1

McBSP->SRGR |=(0x20<<20)|(0x1<<8); //FPER =32 ,FWID=1

McBSP->PCR |=(0x1<<11)|(0x1<<10)|(0x1<<9)|(0x1<<8);

McBSP->XCR =0x104A0;

McBSP->RCR =0x104A0;

McBSP->XCR |=0x1<<18;

McBSP->RCR |=0x1<<18;

while(McBSP->SPCR & 0xC00000);

while(McBSP->SPCR & 0x10001);

McBSP->SRGR =McBSP->SRGR | (0x1<<29); //CLKSM=1

McBSP->PCR &= ~(0x80); //SCLKME=0

wait(2*150);

McBSP->SPCR |=0x1<<22;

wait(2*50);

McBSP->SPCR |= 0x1<<16);

wait(2*50);

if(McBSP->SPCR & (0x1<<19))

McBSP->SPCR &= ~(0x1<<16);

McBSP->SPCR |=0x10001;

}

over 14 years ago

0 Poornima Tom over 14 years ago

Prodigy 120 points

For the above program the o/p what i gt on debugging is given below:

Transmitted value :05

Recieved value:05

Transmitted value :02

Recieved value :40

Transmitted value:03

Recieved value:140

Transmitted value: 06

Recieved value : 02

Also, during 1st reception of data ,the values of registers are given as below:

RRDY =1 , REMPTY=0 & DRR=0x05 after the execution of the step: while(!(McBSP->SPCR & 0x2));

RRDY=0,REMPTY=0 & DRR =0x05 after the execution of step : *dest=McBSP->DRR;

RRDY=0,REMPTY=1 & DRR=0x20 after the execution of step : Printf("Recieved value :\t%02X\n",*dest);

I even tried by configuring FSGM=0.During this case when FSGM=0, On debugging, the program is getting stuck at the step while(!(McBSP->SPCR&0x2)) ; which means that RRDY is not becoming 1 , even in the transmission of 1st data .

Please suggest me on the issue.

0 Miguel A. Alanis over 14 years ago in reply to Poornima Tom

TI__Genius 9490 points

Poornima Tom,

Not sure what could be wrong on your system, I'm attaching a mcbsp DLB polling example testcase, it is not specifically done for this device so it will not run on it, but the MCBSP is the same as the one in this device, so use it for reference to help you track down what's going on wrong on your setup.

please let us know if it helps you cross check your mcbsp specific configuration and data flow setup.

regards,

miguel

mcbsp_polling_example.rtf

0 Poornima Tom over 14 years ago in reply to Miguel A. Alanis

Prodigy 120 points

Hi Miguel,

On giving break points, as i found that RRDY=1, i assumed that RSR/RBR/RJUST is full which means that the next time, i read DRR, i will get the value in RJUST & for the next read, the value of RBR & so on. So i thought of reading DRR thrice before the actual transmitted value goes to DRR.So i wrote the code :

for(i=0;i<3;i++)

{*dest =McBSP->DRR;}

I gave this code just before checking whether RRDY is 1.

ie, before the following code:

while(!(McBSP->SPCR & 0x2));

*dest =McBSP->DRR;

Now the code is working fine.

Thanks,

Poornima Tom

0 Poornima Tom over 14 years ago in reply to Poornima Tom

Prodigy 120 points

Hi Miguel,

When I changed the CLKGDV value from 2 to 4, i found that the value recieved for the first & 2nd time is different but rest of the values were recieved correctly! I was wondering on the relation of ClKGDV. Here the sysclk2 =150 MHZ. Also, FSGM =1, FPER=32 ,FWID =1. Please put a light on this.

Thanks,

poornima Tom

0 Miguel A. Alanis over 14 years ago in reply to Poornima Tom

TI__Genius 9490 points

Poornima Tom,

One thing to note when using FSGM=1(periodic) is that the Mcbsp produces 2 XRDY events back to back when pulling the XRST out of reset (this is helpful for using EDMA in order to quickly start the EDMA transfer to sort of pre-fetch data to have ready for the DXR) When FSGM=0, however you have more control when you generate the XRDY event(XSR-DXR) tranfer. Changing the CLKGDV changes the speed that events take place, so it will cause sometype of impact of course.

regards,

miguel

0 Poornima Tom over 14 years ago in reply to Miguel A. Alanis

Prodigy 120 points

Hi Miguel,

When FSGM=0, are we supposed to do something to make RRDY = 1. I am asking this question because, on giving FSGM =0 , it hangs after 1st transmission in DLB.

while(!(McBSP->SPCR & (ox1<<17))); // XRDY becomes 1

McBSP->DXR = *source; // XRDY=0 ,XEMPTY =1

printf('transmitted value: %X ",McBSP->DXR); // XRDY= 0, XEMPTY =1

while(!(McBSP->SPCR & 0x2)); //prgrm hangs on this line , which means RRDY remains 0. But XRDY =1 & XEMPTY =0

*dest = McBSP->DRR;

Could you please explain me on this.

Thanks,

Poornima Tom

0 Miguel A. Alanis over 14 years ago in reply to Poornima Tom

TI__Genius 9490 points

Poornima,

RRDY becomes a one when data has been received in the DRR register and is ready to be read. I'm not sure why your program code hangs on that particular line. Unless there is something with the way you are polling the correct bit or if the transmitter is not shifting the data from the DXR register and getting looped back in to the DRR.

On this line "while(!(McBSP->SPCR & (ox1<<17))); // XRDY becomes 1"

is that a 'o' or a '0' that you are using to shift the 1 <<17?

One thing to keep in mind when you are debugging via CCS is the 'emulation halt' mode (Free/Soft), ensure that you are free running so the mcbsp clocks don't stop shifting data when you hit an emulation halt.

Here's the example code that I had provided, there is nothing special..

/* Poll for XRDY flag to acknowledge transmitter is ready */

while (!CSL_FEXT(mcbspRegs->SPCR, MCBSP_SPCR_XRDY));

CSL_mcbspWrite (hMcbsp[i], CSL_MCBSP_WORDLEN_32, &xmitBuff[j]);

/* Poll for RRDY flag to acknowledge receiver is ready */

while (!CSL_FEXT(mcbspRegs->SPCR, MCBSP_SPCR_RRDY));

CSL_mcbspRead (hMcbsp[i], CSL_MCBSP_WORDLEN_32, &rcvBuff[j]);

regards,

miguel

Processors

Processors forum

McBSP-Digital loop back mode issue