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Using SRIO on EVM6455

chunliang lee
Prodigy 20 points

I have do the srio boot of digitalspetrum c6455 evm two weeks, nearly config all reg of srio relative,stil a lot of problem there.

I can connect host to slave,but failed to write and read to slave's memory!

lcaliang@hotmail.com

It's surely the EVM6455 with mezzanine card ,zhe host processor is TI'c6455.

I just want to have more members join to this topic ,share experience and provide help to each others.

now a few fproblem is confusing me:

(1) in sprz976b.pdf, is 1x/4x stand for 1port and 4lane? is 1x/1x meas 1port and 1 lane? 4x/1x means 4port and 4 lane?

(2) to srio ,the peak rate is 3.125Gb/s, so the peak rate of 1x/4x will be 12.5Gb/s, 4x/1x 's wiil be 12.5 too, and 1x/1x's will be 3.125,right?

(3) is  the peak rate 3.125Gb/s  unidirectional ? if  be bilateral ,should rate be doubled? 6.25

(3) in sprz976.pdf ,the 31-30bit of IP_mode_reg are R/W,why I can't write value to them?

thanks for your attention, I truely look forward to your help

  • 0
    TI__Guru* 84110 points

    In the Technical Training Organization's IW6455 class has a module that discusses the SRIO peripheral. It also includes a lab that demonstrates communicating between the two C6455s using SRIO DirectIO. I have zipped this lab and attached it to this posting. There is also an excerpt from the course material that discusses the steps required to go through the lab - "iw6455m09 Using SRIO lab.pdf". Please try this lab to see if you can get communications working between your two DSPs.

    chunliang lee said:

    (1) in sprz976b.pdf, is 1x/4x stand for 1port and 4lane? is 1x/1x meas 1port and 1 lane? 4x/1x means 4port and 4 lane?

     

    There is no document I can find named sprz976b.

    The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the RapidIO Physical Layer 1x/4x LP-Serial Specification. These and the various associated documents listed herein can be found at the official RapidIO website: www.RapidIO.org. "1x/4x" and "1x/1x" are defined in these specifications and are not specific to TI's SRIO peripheral. Please refer to the original documentation at that website.

    You will see some terms used in the TI documentation that use 4p1x to refer to 4 ports of 1x speed and 1p4x to refer to 1 combined port running at 4x speed.

    chunliang lee said:

    (2) to srio ,the peak rate is 3.125Gb/s, so the peak rate of 1x/4x will be 12.5Gb/s, 4x/1x 's wiil be 12.5 too, and 1x/1x's will be 3.125,right?

    Again, the terms you use are not right. You would use 1p for one port or 4p for 4 ports. But you have the right idea with the combined physical bit rate. Of course, this is not the same as the data rate because of 8b/10b coding and SRIO packet overhead. But you have the right idea from the high level.

    chunliang lee said:

    (3) is  the peak rate 3.125Gb/s  unidirectional ? if  be bilateral ,should rate be doubled? 6.25

    The bit rate of 3.125Gb/s is for each Tx or Rx path. Both Tx and Rx can be operating simultaneously at 3.125Gb/s. This is refereed to as one lane running at 3.125Gb/s.

    chunliang lee said:

    (3) in sprz976.pdf ,the 31-30bit of IP_mode_reg are R/W,why I can't write value to them?

    Since there is no register named IP_mode_reg, you may be trying to access the wrong location when you try to write. Exact names and terms will make a technical discussion easier.

    SRIO_MasterSlave_DIO.zip