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Original question:

TDA4VM: TDA4 hang on uboot when uart print "Timeout during frequency hands"

TDA4VM: Modify DDRSS_PHY_33,289,545,801 means what parameters are modified

Peggie Wang
Prodigy 30 points
Part Number: TDA4VM

Hi  Kevin,

I had a similar issue with TDA4VM with LPDDR4X 4266MHz.

After searching e2e, based on this case your suggestion, #define DDRSS_PHY__33,289,545,801_DATA 0x0C002006, change the '7' to a '6', and my problem was well solved.

But I still have some questions, DDRSS_PHY_33,289,545,801 means what parameters were modified and why, this I did not find the information and can not understand.

Please help to answer, thank you very much.

 

e2e.ti.com/.../3897047

  • 0
    TI__Mastermind 38600 points

    Hi Peggie,

    This parameter defines the data pattern used during write DQ training. There are 4x registers as the pattern has to be programmed for each byte lane.

    This change was actually made permanent in version 0.6.1 of the Jacinto7 DDR Register Config Tool (https://www.ti.com/lit/pdf/spracu8 ). 

    1) Updated write DQ training pattern (from 0x7 to 0x6) to prevent invalid training results observed in some systems
        - Register Updates
            > DDRSS_PHY_33, PHY_WDQLVL_PATT_0
            > DDRSS_PHY_289, PHY_WDQLVL_PATT_1
            > DDRSS_PHY_545, PHY_WDQLVL_PATT_2
            > DDRSS_PHY_801, PHY_WDQLVL_PATT_3