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Original question:

TDA4VM: TDA4VM: Which boot mode should I set to run keywriter

TDA4VM: TDA4VM: Is there a patch for keywriter to output logs when boot from SD card ?

zmite
Prodigy 230 points
Part Number: TDA4VM

Hi Experts,

    According to  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1119578/tda4vm-tda4vm-which-boot-mode-should-i-set-to-run-keywriter/4167869?tisearch=e2e-sitesearch&keymatch=keywriter#4167869

    I meet the same problem, when boot from SD card, no logs on uart. but when boot from UART, I can see keywriter's log.

    in that title, seems like there is a patch to enable keywriter output on sd boot mode,  from TI's experts.  can you provide it ? thanks.

  • 0
    Prodigy 230 points

    well, rewriter uart init code in kerywriter, debug log can output to mcu_uart0.

  • 0 in reply to zmite
    TI__Expert 5000 points

    Great. Thanks for you confirming. 

  • 0 in reply to Fredy Zhang
    TI__Guru**** 162990 points

    Fredy,

    Can we close this as the resolved is clicked?

    - Keerthy

  • +1 in reply to Keerthy J
    TI__Expert 5000 points

    Keerthy, 

    Close this ticket. SDK8.0 UART clock didn't work. Pleaser refer to below change to enable the clock . 

    ubuntu:~/tda4vm-08-00/ti-processor-sdk-rtos-j721e-evm-08_00_00_12/pdk_jacinto_08_00_00_37/packages/ti$ git diff boot/keywriter/main.c
diff --git a/packages/ti/boot/keywriter/main.c b/packages/ti/boot/keywriter/main.c
index 3fea7d7..202b98b 100644
--- a/packages/ti/boot/keywriter/main.c
+++ b/packages/ti/boot/keywriter/main.c
@@ -180,13 +180,37 @@ static void mmr_unlock(uint32_t base, uint32_t partition){
        HW_WR_REG32(part_base + CTRLMMR_LOCK_KICK1, CTRLMMR_LOCK_KICK1_UNLOCK_VAL);
 }
 
+#define SBL_UART_PLL_BASE                   (CSL_MCU_PLL0_CFG_BASE)
+#define SBL_UART_PLL_KICK0_OFFSET           (CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0)
+#define SBL_UART_PLL_KICK1_OFFSET           (CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY1)
+#define SBL_UART_PLL_DIV_OFFSET             (CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL3)
+#define SBL_UART_PLL_DIV_VAL                (0x00008031)
+#define SBL_UART_PLL_KICK0_UNLOCK_VAL       (0x68EF3490)
+#define SBL_UART_PLL_KICK1_UNLOCK_VAL       (0xD172BC5A)
+#define SBL_UART_PLL_KICK_LOCK_VAL          (0x0)
+
+static void J721E_UART_InitPwrClk(void)
+{
+    HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_KICK0_OFFSET, SBL_UART_PLL_KICK0_UNLOCK_VAL);
+    HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_KICK1_OFFSET, SBL_UART_PLL_KICK1_UNLOCK_VAL);
+
+    HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_DIV_OFFSET, SBL_UART_PLL_DIV_VAL);
+
+    HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_KICK0_OFFSET, SBL_UART_PLL_KICK_LOCK_VAL);
+    HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_KICK1_OFFSET, SBL_UART_PLL_KICK_LOCK_VAL);
+}
+
+
+
 int main()
 {
        int32_t status = CSL_EFAIL;
        uint32_t debug_response = 0;
        uint32_t *keywriter_cert = &keywr_end + 1;
        UART_HwAttrs uart_cfg;
-       
+
+       J721E_UART_InitPwrClk();
+
        /* padconfig unlock */
        mmr_unlock(WKUP_CTRL_BASE, 7);
        /* pinmux for R5 logs */
     

    Regards, 

    Fredy Zhang