TDA4VM: Register Offset for SerDes

H@fiz

Part Number: TDA4VM

I am working on PCIe0 on TDA4VMXEVM. While exploring the thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally?tisearch=e2e-sitesearch&keymatch=routing%20refclk%20externally

I can see a patch: /cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_route_2D00_clock_2D00_externally.patch

Can you confirm the registers offset

>>> static const struct reg_field cmn_plllc_clk1outdiv = REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
Is it register "CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG" having address 0x05000098
"CMN_PLLLC_LOCK_CNTTHRESH_PREG" is 12 bit field but REG_FIELD filed describes 0-6 bits. Kindly confirm.

>>> static const struct reg_field cmn_plllc_clk1_en = REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);
Is it register "CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG" having address 0x05000098
"CMN_PLLLC_LOCK_CNTTHRESH_PREG" is 12 bit field but REG_FIELD filed describes bit 12. Kindly confirm.

>>> static const struct reg_field phy_pma_cmn_ctrl_rcv_out_en = REG_FIELD(PHY_PMA_CMN_CTRL1, 6, 7);
Is it register "PHY_PMA_CMN_CTRL2__PHY_PMA_CMN_CTRL1" having address 0x0505E000. Kindly confirm.

>>> static const struct reg_field phy_pll_cfg_1 = REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
Is it register "PHY_AUTO_CFG_CTRL__PHY_PLL_CFG" having address 0x0500C01C. Kindly confirm.

>>> static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); // Page 3872, To Do
Is it register "PLLLNC_STATUS_PREG__PLLCTRL_STATUS_PREG_j" having address 0x05004088 + (j * 0x400) where j = 0 to 1

Regards

over 3 years ago

0 jian35385 over 3 years ago

TI__Mastermind 23125 points

HUQ:

SERDES registers are 16-bit wide in its native form. But two adjacent registers are combined in the TRM, as all registers in the TRM are defined as 32-bit wide. Using the first question you raised as an example, the PHY_PMA_CMN_CTRL1 is the first half of the TRM register CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG, the the correct TRM field description should be:

CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG[CMN_PLLLC_CLK1OUTDIV_PREG]

The driver code translates these "half" registers to the correct SOC address.

I see the rest of your question are due to the same issue. so will not answer them one by one. Please let me know if you still have doubts.

Jian

0 H@fiz over 3 years ago in reply to jian35385

Intellectual 440 points

Thanks Jian for your prompt response. It really helps. Updated the patch for PCIe0/SerDes0 (Note that we are not using linux)

temp32 = READ32(0x05000000 + 0xC01C); // PHY_AUTO_CFG_CTRL__PHY_PLL_CFG
temp32 |= (1<<1); // PHY configured to use both PLL LC and LC1
WRITE32(0x05000000+ 0xC01C, temp32);

//WRITE32(0x0505E000, 3<<6); // Not required for PCIe0/SerDes0; Only for SERDES_10G0

// Based on Jian Comment: e2e.ti.com/.../3348028

temp32 = READ32(0x05000000+ 0xe000);// PHY_PMA_CMN_CTRL
temp32 |= (1<<6); // Drives cmn_refclk_rcv_out_en PMA input
WRITE32(0x05000000+ 0xe000, temp32);

temp32 = READ32(0x05000098);//CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG
temp32 |= ((1<<28) | (0x2e<<16));
WRITE32(0x05000098, temp32);

WRITE32(0x00118090, 0x01000000);// CTRLMMR_ACSPCIE0_CTRL
WRITE32(0x00105008, 0x68EF3490);// CTRLMMR_LOCK1_KICK0
WRITE32(0x0010500C, 0xD172BC5A);// CTRLMMR_LOCK1_KICK1

WRITE32(0x00108070, 0x00000100);// CTRLMMR_PCIE_REFCLK0_CLKSEL

Can you confirm the bold section?

0 jian35385 over 3 years ago in reply to H@fiz

TI__Mastermind 23125 points

HUQ,

You should not need to set the 0x0500e000 register. Bit 6 and 7 enables output of cmn_refclk_n, it is not relevant to your case.

Jian

0 H@fiz over 3 years ago in reply to jian35385

Intellectual 440 points

Thanks Jian for your response. Appreciated

This resolves my issue.

A question related to TRM:

I can't see the description of "P0_STANDARD_MODE" of "SERDES_ LANECTL0" register in TRM. Can you provide details of these bits OR can you confirm the value (For PCIe0 on TDA4VMXEVM board - X1 Lane - I have set the value 2).

FYI: I have set CTRLMMR_PCIE0_CTRL = 0x82 (PCIe0 Root Complex, 1 Lane and Gen3)

0 H@fiz over 3 years ago in reply to H@fiz

Intellectual 440 points

Hi Jian,

Have you get time to see above question?

0 jian35385 over 3 years ago in reply to H@fiz

TI__Mastermind 23125 points

HUQ,

I have answered the question about P0_STANDARD_MODE in the other thread you created:

(8) J721EXSOMXEVM: Missing Pin Control DTS Property in PCIe Node - Processors forum - Processors - TI E2E support forums

and I also checked my board, these bits shall be left as 0.

regards

jian

0 H@fiz over 3 years ago in reply to jian35385

Intellectual 440 points

Hi Jian,

Thanks for providing information regarding "P0_STANDARD_MODE" in another thread.

but i am unable to understand rest of the comment >>> and I also checked my board, these bits shall be left as 0.

+1 jian35385 over 3 years ago in reply to H@fiz

TI__Mastermind 23125 points

HUQ,

in the other thread, i looked up that:

P0_STANDARD_MODE in our document, it was defined as "Standard Mode specified by Cadence."

So suspected that this field is used if the SERDES needs to support any raw modes defined by Cadence. Since I was not ablet to get the actual definition of the Cadence mode, I checked my working EVM, and confirmed these bits shall be left as default and not be programmed.

regards

Jian

0 H@fiz over 3 years ago in reply to jian35385

Intellectual 440 points

Hi Jian,

I can see (using devmem2) the value 3 (equals to LANE_MODE_GEN4 - This is not a default or reset value) for these bits (P0_STANDARD_MODE) after the execution of lspci command. It is also confirmed from "wiz_mode_select" function.

Thanks.