C6748 boot fails when code placed in DDR

Admar Schoonen

Well, it seems there is still an error (likely again between keyboard and chair, but this time I can't seem to find it).

I did succeed in booting the C6748 SOM on the EVM and running the keystone example from IRAM. I even succeed in configuring PLL0, PLL1 and DDR in AISgen and booting and running the example from IRAM. However, as soon as I place the code section (.text) in DDR, the program won't run anymore. If I connect the debugger, the CPU is stuck at 0x11804408 (BNOP.S1):

SYS_EXITFXN, UTL_halt:
0x11804400: 01BC54F7 STW.D2T2 B3,*SP--[2]
0x11804404: 1FFF7812 || CALLP.S2 _HWI_disable (PC-1088 = 0x11803fc0),B3
C$L1:
0x11804408: 0002A120 BNOP.S1 C$L1 (PC+8 = 0x11804408),5
0x1180440C: 00000000 NOP
0x11804410: 00000000 NOP
0x11804414: 00000000 NOP
0x11804418: 00000000 NOP
0x1180441C: 00000000 NOP
CLK_TIMEFXN, CLK_F_gethtime, _CLK_gethtime:

My AISgen config file is: , my tcf file is: , and the generated bin file is: . (Remove .jpg extensions from files.)

Any help is appreciated!

Admar

over 14 years ago

0 Brad Griffis over 14 years ago

TI__Guru*** 125430 points

Admar,

It looks like control has transferred from the boot ROM to your application code. The primary thing that changes when moving from a CCS environment to a stand-alone environment is that you will no longer have the gel file to configure things for you ahead of time. If you look in the gel file you'll see it's doing things such as:

Enable all PSC domains
PLL0 and PLL1 configuration
mDDR configuration

I imagine your issue is ultimately due to something not being properly configured in AISgen. In other words, something that previously was being done by the gel file is no longer being done, which is causing your application to crash.

Please read the following wiki page carefully as it gives some very specific tips/methods for debugging your application after it has booted from flash:

http://processors.wiki.ti.com/index.php/Debugging_Boot_Issues

You ought to be able to step through the code in CCS and see at exactly what point it fails. The way in which it fails (DDR access, peripheral access, etc) should give you a hint as to the root cause of the failure.

Brad

0 Admar Schoonen over 14 years ago in reply to Brad Griffis

Intellectual 480 points

Hi Brad

Thanks for moving this to this thread. (For archive reasons: the previous thread is here.)

I've made some progress today. According to the manual from Lab 14a, you need to configure PLL0, PLL1 and DDR in AISgen if you want to run code from DDR memory. I was under assumption that in that case, you would still need to call EVMC6748_init() and EVMC6748_initRAM() in main(). It turns out that the EVMC6748_init() was causing me problems. Specifically, this function calls init_clocks() which configures PLL0 and PLL1 again, and the PLL1 configuration caused some kind of conflict:

uint32_t init_clocks(void)
{
uint32_t rtn;

// unlock the system config registers.
SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;

rtn = config_pll0(0,24,1,0,1,11,5);
rtn |= config_pll1(24,1,0,1,2); // <-- this line is suspect!

// enable 4.5 divider PLL and set it as the EMIFA clock source.
// SETBIT(SYSCONFIG->CFGCHIP[3], DIV4P5ENA | EMA_CLKSRC);

return (rtn);
}

This function is from C:\TI\ccsv4\emulation\boards\evmc6748_v1-1\bsl\src\evmc6748.c. It doesn't have a version number and I'm not sure how I got it on my computer, but it is dated 7-7-2010 13:55 (like all other files in that directory).

If I remove the config_pll1() line, I can successfully run both my little test application and the keystone example from DDR memory and booting from flash!

I have a few questions now:

1. If you configure PLL0, PLL1 and DDR in AISgen, do you still need to call EVMC6748_init() and EVMC6748_initRAM()?

2. Do I perhaps have an outdated version of the bsl? How can I find out which version I have and where can I find updates?

I have also partially succeeded in running my custom DSP application from flash. With above changes, it hung in PMI_waitT1 / PMI_writeI2C in pmi_i2c.c. This looks pretty much like this issue. Turning off V/F scaling in the PWRM module in .tcf solved it for me as well. My application now boots from flash and runs from DDR and sampling from the ADC works (verified with oscilloscope). It only fails to send the output to the UART, but that could perhaps be a Pinmux issue.

Anyway, if you can answer my questions, I think we can close this topic.

Thank you very much for your help!

0 Admar Schoonen over 14 years ago in reply to Admar Schoonen

Intellectual 480 points

Just a small update: the UART was not a Pinmux issue. I had to enable the UART in PSC (put '13' in the PSC1 field in the PSC tab in AISgen). My custom DSP application is now booting from flash and running from DDR and everything is working fine.

The next big thing is trying to get this setup working on our custom board...

0 Brad Griffis over 14 years ago in reply to Admar Schoonen

TI__Guru*** 125430 points

Admar Schoonen said:
I was under assumption that in that case, you would still need to call EVMC6748_init() and EVMC6748_initRAM() in main(). It turns out that the EVMC6748_init() was causing me problems. Specifically, this function calls init_clocks() which configures PLL0 and PLL1 again, and the PLL1 configuration caused some kind of conflict

You should not call either of those functions as they will have a destructive behavior on the DDR, i.e. you will lose anything already in the DDR (like your code!).

Although in general I like the way Logic structured their code, this particular choice with the "#ifdef NO_GEL" is one thing that I dislike. In my opinion the proper way to do the development is:

When developing from CCS, you should have a gel file to configure PLLs and DDR. CCS of course loads the code.
When switching to a stand-alone system (boot from flash), then the responsibility of configuring PLLs, DDR, and loading code will shift to the boot loader.

So in neither case does the application ever handle configuration of PLLs and DDR. This would be done by either CCS or the bootloader depending on where you're at in your development.

Admar Schoonen said:
It only fails to send the output to the UART, but that could perhaps be a Pinmux issue.

I would look at both PSC and pinmux. The OMAP-L1x debug gel file can help you very quickly determine the PSC state for the UARTs. You should be able to look in the register window to see if the pinmux settings are correct.

0 Admar Schoonen over 14 years ago in reply to Brad Griffis

Intellectual 480 points

Brad,

Thanks for your answers. I have removed all calls to EVMC6748_init() and EVMC6748_initRAM() from my code, and it indeed still boots and runs correctly.

Please update Lab14a (step 7?) in the materials of "C6000 Embedded Design Workshop using BIOS", since it is confusing (at least it was for me).

Thanks for your help.

Admar

0 Brad Griffis over 14 years ago in reply to Admar Schoonen

TI__Guru*** 125430 points

Admar Schoonen said:

Please update Lab14a (step 7?) in the materials of "C6000 Embedded Design Workshop using BIOS", since it is confusing (at least it was for me).

Good observation... The project from the workshop doesn't define "NO_GEL" anywhere, so that code is not compiled into the executable. Now that the lab is taking on new life/purpose outside the confines of the class room, this would be a good thing to explicitly mention in the procedure, i.e. that we do NOT want that code compiled into the executable since we will have the boot ROM perform that initialization based on values we specify inside AISgen.

I have passed on your comments to the workshop author, so I imagine that will get modified in the next version of the workshop. (If it was a wiki page I would have already changed it!)

0 Admar Schoonen over 14 years ago in reply to Brad Griffis

Intellectual 480 points

For other users who might stumble upon the same problem: here is my AISgen config file: (remove .jpg extension)

This is for d800k002 DSP (silicon rev 1), and sets up PLL0, PLL1, DDR and PSC.

The "corresponding" GEL file is (remove .jpg extension). Note that I've modified this file so that it does not automatically set up all these things when you connect. Instead, you have to do this explicitly via Scripts -> TargetConnect -> TargetConnect. The advantage is that you can then connect to a running DSP and inspect what it's doing without messing up some settings.

This setup works for me with the Logic EVM with C6748 SOM, boot from SPI flash and using SPI1, some GPIO and UART2 in my custom application. There is no need to call EVMC6748_init() or EVMC6748_initRAM() in the DSP application.

Admar

0 George Paravas over 13 years ago in reply to Admar Schoonen

Intellectual 280 points

Dear Admar & Brad,

I have the same problem with the DSP/BIOS but I do not call any of the functions that Admar has called. I have built a simple hello program, when I run it using the Gel file everything works, when I boot through the UART the program does not start. I have checked my DDR and the code (the codes that the AIS has generated) is in DDR with the same sequence as it appears in the AIS.bin file. However the program counter seems to stop/halt within the bootloader area, in memory locations above 0x00700000 but within the 1024K memory space of the L2 ROM.

And although booting from UART succeeds (CRC passes) and at the end I get the (AIS complete. Jump to address 0xC001ED20). 0xC001ED20 in one of the examples is the location of the c_int00, Nothing happens after that. I must say that a different (again simple example) without the DSP/BIOS works fine with the GEL and also when booting from UART.

The memory location within the rom that the program counter jumps to is: 0x007F5D4C: BC85 STW.D2T2 B0,*B15[5]

the device version is: d800k006.

P.S: I also tried to specify an entrypoint in the AIS, in an assumption that it might unblock the DSP, and I noticed In another post that, In order to change the entry point for a .out, you must rebuild it with the modified linker.cmd file. But I do not know how to modify the linker.cmd file to make the P.C. to jump to a memory location that I want.

Any ideas will be greatly appreciated,

Thanks ,

George.

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

Make sure you're not enabling SATA in the AIS PSC settings. That will cause the boot loader to hang.

After the device fails to boot you should connect with JTAG using the following gel file and dump the corresponding info:

http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files

0 RandyP over 13 years ago in reply to Brad Griffis

TI__Guru* 84110 points

Please note that George's post is also at http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/179331.aspx .

0 George Paravas over 13 years ago in reply to Brad Griffis

Intellectual 280 points

Dear Brad,

After solving some other critical issues I'm continuing with this issue now, with regarss to the above, I have had the SATA disabled.

I have retested the whole issue and I have used a simple application that after booting from UART1 send a string to UART2 to indicate that the application runs. However, after sucessful (crc is shown as passed) boot from UART the aplication does not run when I use the DDR (configured from AISgen). The same application runs fine when I use the IRAM.

And as before, when I use the CCS to download the code to the DSP the application always works with both IRAM & DDR.

I have run the gel file you've suggested but I do not see any indication as to the problem cause.

any suggestions?

thanks,

George.

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

Please do the following:

Attempt to boot to DDR like you've been doing
Connect to the board with only the OMAP-L1x Debug Gel File loaded.
Do the "run all" test.
Copy/paste the CCS output into a file, e.g. output.txt
Attach that file here (under "Options" up above the previous post when composing)

The other thing you should do is follow the suggestions provided here to debug:

http://processors.wiki.ti.com/index.php/Debugging_Boot_Issues

So in particular you should be able to:

Connect to target with NO gel file.
Perform system reset by going to Run -> Reset -> System Reset
Load SYMBOLS for your application
Set HARDWARE breakpoint at c_int00.
Run -> Run
Download your program over UART as usual, i.e. it will look to the host computer like you just came out of reset (since you did!)

After step 5 if the UART loading was truly successful you should now be halted at the entry point to your application as loaded by the bootloader. Before you do anything look in a disassembly window to see if it looks "normal". (You should not see ".word" assignments in the disassembly window. If you do it means there are unrecognized opcodes which is bad.) Also look at the same address area in the memory window. If you refresh a few times hopefully you don't see anything changing, i.e. DDR configuration is stable. If you're still good at this point then continue stepping through the code until you figure out where things go wrong...

0 George Paravas over 13 years ago in reply to Brad Griffis

Intellectual 280 points

{This post has been eddited with extra info please see below}

Dear Brad,

Thanks for the reply, the first part you've asked is this (i've tried to attach the file but it wasn't succesful so I've pasted here):

=====================================================================================================================

Dear Brad,

I've re-booted the application from UART (via UART boot Host utility) without power cycling the board, and this time the results are different (see below):

======================================================================================================================

C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000017
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5621784-16-14-17
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,2930
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x1001100E
C674X_0: GEL Output: DEV_INFO_25 = 0x0055C818
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x16E40002
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot pins: 23
C674X_0: GEL Output: Boot Mode: UART1C674X_0: GEL Output: , 24 MHz or 12 MHz input clock
C674X_0: GEL Output:
ROM Status Code: 0x00000000
Description:C674X_0: GEL Output: No error
C674X_0: GEL Output:
Program Counter (PC) = 0x007F5D4C
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 25 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 8 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 8 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 25 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 25 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 25 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:   EDMA3CC (0)        STATE = 0
C674X_0: GEL Output: Module 1:   EDMA3 TC0          STATE = 0
C674X_0: GEL Output: Module 2:   EDMA3 TC1          STATE = 0
C674X_0: GEL Output: Module 3:   EMIFA (BR7)        STATE = 0
C674X_0: GEL Output: Module 4:   SPI 0              STATE = 0
C674X_0: GEL Output: Module 5:   MMC/SD 0           STATE = 0
C674X_0: GEL Output: Module 6:   AINTC              STATE = 0
C674X_0: GEL Output: Module 7:   ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9:   UART 0             STATE = 0
C674X_0: GEL Output: Module 10:   SCR 0 (BR0/1/2/8) STATE = 3
C674X_0: GEL Output: Module 11:   SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12:   SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13:   PRUSS              STATE = 0
C674X_0: GEL Output: Module 14:   ARM                STATE = 0
C674X_0: GEL Output: Module 15:   DSP                STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:   EDMA3CC (1)        STATE = 0
C674X_0: GEL Output: Module 1:   USB0 (2.0)         STATE = 0
C674X_0: GEL Output: Module 2:   USB1 (1.1)         STATE = 0
C674X_0: GEL Output: Module 3:   GPIO               STATE = 0
C674X_0: GEL Output: Module 4:   UHPI               STATE = 0
C674X_0: GEL Output: Module 5:   EMAC               STATE = 0
C674X_0: GEL Output: Module 6:   DDR2 and SCR F3    STATE = 0
C674X_0: GEL Output: Module 7:   MCASP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 8:   SATA               STATE = 0
C674X_0: GEL Output: Module 9:   VPIF               STATE = 0
C674X_0: GEL Output: Module 10:   SPI 1              STATE = 0
C674X_0: GEL Output: Module 11:   I2C 1              STATE = 0
C674X_0: GEL Output: Module 12:   UART 1             STATE = 3
C674X_0: GEL Output: Module 13:   UART 2             STATE = 0
C674X_0: GEL Output: Module 14:   MCBSP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 15:   MCBSP1 + FIFO      STATE = 0
C674X_0: GEL Output: Module 16:   LCDC               STATE = 0
C674X_0: GEL Output: Module 17:   eHRPWM (all)       STATE = 0
C674X_0: GEL Output: Module 18:   MMC/SD 1           STATE = 0
C674X_0: GEL Output: Module 19:   UPP                STATE = 0
C674X_0: GEL Output: Module 20:   eCAP (all)         STATE = 0
C674X_0: GEL Output: Module 21:   EDMA3 TC2          STATE = 0
C674X_0: GEL Output: Module 24:   SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25:   SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26:   SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27:   SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28:   SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29:   SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30:   Br-F7 (DDR Contr) STATE = 3
C674X_0: GEL Output: Module 31:   L3 RAM, SCR-F4, Br-F6 STATE = 3
C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000017
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5621784-16-14-17
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,2930
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x1001100E
C674X_0: GEL Output: DEV_INFO_25 = 0x0055C818
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x16E40002
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot pins: 23
C674X_0: GEL Output: Boot Mode: UART1C674X_0: GEL Output: , 24 MHz or 12 MHz input clock
C674X_0: GEL Output:
ROM Status Code: 0x00000000
Description:C674X_0: GEL Output: No error
C674X_0: GEL Output:
Program Counter (PC) = 0xC00003E4
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 25 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:   EDMA3CC (0)        STATE = 3
C674X_0: GEL Output: Module 1:   EDMA3 TC0          STATE = 3
C674X_0: GEL Output: Module 2:   EDMA3 TC1          STATE = 3
C674X_0: GEL Output: Module 3:   EMIFA (BR7)        STATE = 3
C674X_0: GEL Output: Module 4:   SPI 0              STATE = 3
C674X_0: GEL Output: Module 5:   MMC/SD 0           STATE = 3
C674X_0: GEL Output: Module 6:   AINTC              STATE = 0
C674X_0: GEL Output: Module 7:   ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9:   UART 0             STATE = 3
C674X_0: GEL Output: Module 10:   SCR 0 (BR0/1/2/8) STATE = 3
C674X_0: GEL Output: Module 11:   SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12:   SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13:   PRUSS              STATE = 0
C674X_0: GEL Output: Module 14:   ARM                STATE = 0
C674X_0: GEL Output: Module 15:   DSP                STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:   EDMA3CC (1)        STATE = 3
C674X_0: GEL Output: Module 1:   USB0 (2.0)         STATE = 3
C674X_0: GEL Output: Module 2:   USB1 (1.1)         STATE = 3
C674X_0: GEL Output: Module 3:   GPIO               STATE = 3
C674X_0: GEL Output: Module 4:   UHPI               STATE = 3
C674X_0: GEL Output: Module 5:   EMAC               STATE = 3
C674X_0: GEL Output: Module 6:   DDR2 and SCR F3    STATE = 3
C674X_0: GEL Output: Module 7:   MCASP0 + FIFO      STATE = 3
C674X_0: GEL Output: Module 8:   SATA               STATE = 0
C674X_0: GEL Output: Module 9:   VPIF               STATE = 3
C674X_0: GEL Output: Module 10:   SPI 1              STATE = 3
C674X_0: GEL Output: Module 11:   I2C 1              STATE = 3
C674X_0: GEL Output: Module 12:   UART 1             STATE = 3
C674X_0: GEL Output: Module 13:   UART 2             STATE = 3
C674X_0: GEL Output: Module 14:   MCBSP0 + FIFO      STATE = 3
C674X_0: GEL Output: Module 15:   MCBSP1 + FIFO      STATE = 3
C674X_0: GEL Output: Module 16:   LCDC               STATE = 3
C674X_0: GEL Output: Module 17:   eHRPWM (all)       STATE = 3
C674X_0: GEL Output: Module 18:   MMC/SD 1           STATE = 3
C674X_0: GEL Output: Module 19:   UPP                STATE = 3
C674X_0: GEL Output: Module 20:   eCAP (all)         STATE = 3
C674X_0: GEL Output: Module 21:   EDMA3 TC2          STATE = 3
C674X_0: GEL Output: Module 24:   SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25:   SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26:   SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27:   SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28:   SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29:   SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30:   Br-F7 (DDR Contr) STATE = 3
C674X_0: GEL Output: Module 31:   L3 RAM, SCR-F4, Br-F6 STATE = 3

If we trust the PC value as returned by the GEL file, we are in the DDR memory space and we are trapped in an endless loop that exist in a source code:

while (CHKBIT(psc->MDSTAT[in_module], MASK_STATE) != in_next_state) {}

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

George Paravas said:

If we trust the PC value as returned by the GEL file, we are in the DDR memory space and we are trapped in an endless loop that exist in a source code:

while (CHKBIT(psc->MDSTAT[in_module], MASK_STATE) != in_next_state) {}

Ok, now you're getting somewhere.. Looks like the application booted but then gets stuck. So first of all, why are you doing power state transitions in your application? Why aren't you having the boot ROM do that (i.e. through AISgen)? I would get rid of that altogether, though another option is to look more closely at what domain is failing to transition. If that's the SATA you have to use the FORCE bit.

0 George Paravas over 13 years ago in reply to Brad Griffis

Intellectual 280 points

Dear Brad,

thanks for the reply.

It might be redundant to transition power states, but the same code from the IRAM runs without any problems, i.e. it doesn't get stuck to the endless loop. Does this give any indications?

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

At a minimum you need to tell me which power domain is being transitioned that gets stuck. If your code does anything to interfere with the DDR that will almost certainly break things. For example, you should NOT be doing any manipulations of the PLLs or DDR configuration.

0 George Paravas over 13 years ago in reply to Brad Griffis

Intellectual 280 points

the condition we use is the following, that initialises uart2, and we boot from uart:

EVMC6748_lpscTransition(PSC1, DOMAIN0, LPSC_UART2, PSC_ENABLE);

Should we have observed the same behaviour when the code is loaded in the IRAM? and if so why is that?

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

I don't see any obvious reason why that function would behave different when executing from DDR vs IRAM. I expect the issue is somewhere else. What else is different between the two cases?

0 George Paravas over 13 years ago in reply to Brad Griffis

Intellectual 280 points

Dear Brad,

There are no other differences between the two cases. we modifiy the load memory of the executble (.text section) code in the command linker file.

0 Brad Griffis over 13 years ago in reply to George Paravas

TI__Guru*** 125430 points

George,

You need to poke around and figure out what's going on. For example:

Does it consistently fail at that exact same place?
Are you enabling other power domains? If so, do any of those actually transition correctly?
Have you tried enabling that domain through the bootloader using the AISgen utility?
Can you simplify the program further to get something that works consistently from DDR?
If you inspect the PSC registers just before that function call what do you see? Anything "strange"? Anything values that differ between the DDR case and the IRAM case?

Brad

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C6748 boot fails when code placed in DDR