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I was looking the code about cpufreq init in da850.c (latest PSP kernel linux-03.21.00.04) and I saw that PLL1_SYSCLK3 is used for the bypass clock for PLL0.
That code seems to have been merged from this patch:
http://arago-project.org/git/projects/?p=linux-davinci.git;a=commitdiff;h=023812881d2592a4aceb1900cc4ff9c13473b1f3;hp=866e696b239a484e10e81a00d2ed89e8bd4c33ba
which has the following log comment:
"The patch modifies the PLL0 bypass clock source to PLL1_SYSCLK3
by setting the EXTCLKSRC bit in PLL0 PLLCTL register. Without
this patch, PLL0 bypass clock is at 24MHz.
For some peripherals, the module clock must be greater than a
particular value for proper operation. But during DVFS when PLL
is put in bypass mode, the module clock will be below the specified
limit. For example: the USB0 controller module clock must be greater
than 30 MHz for proper operation of USB controller. But during DVFS,
USB0 module clock will be at 12 MHz (PLL0_INPUT/2) causing USB data
starvation. PLL0 clock rate of 60 MHz or greater is recommended to
avoid data throughput reduction.
Configuring the bypass clock source as PLL1_SYSCLK3, PLL0 will be
at 88 MHz during PLL bypass and USB module clock will be 44 MHz."
The last two lines really puzzle me, because reading AM1808 documentation it seems not possible to get clocks above 50Mhz from PLL1_SYSCLK3 !
Tell me if I'm wrong, but according to the schema in the datasheet AM1808.pdf http://www.ti.com/lit/gpn/am1808 section 5.6.1, page 79, when the bit EXTCLKSRC is set in PLLCTL, the clock from PLL1_SYSCLK3 is fed directly to the PLLDIV1-7.
USB is clocked from SYSCLK2, which is always at a fixed ratio of (SYSCLK1 / 2).
So needing 44MHz for USB means that SYSCLK1 must be at 88MHz and even with PLLDIV1 set to 1 this implies that PLL1_SYSCLK3 should be set to 88MHz.
But at page 81 of the same datasheet it is clearly stated that the maximum allowed frequency for PLL1_SYSCLK3 as an alternate clock source for PLL0 is 50MHz.
I've also downloaded the Clocking Check Spreadsheet from http://processors.wiki.ti.com/index.php/Programming_PLL_Controllers_on_OMAP-L1x8/C674x/AM18xx and found no way to obtain more than 50MHz for SYSCLK1 (==25MHz for SYSCLK2/USB clock) using PLL1_SYSCLK3 as a clock source.
So what am I missing here?
Thank in advance for the reply. Gabriele.
