[FAQ] AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 Custom board hardware design - Reusing TI SK (EVM) design files

Hi Board designers, 

For the purpose of faster prototype development, minimizing errors, optimizing efforts, you could consider reusing the EVM collaterals and is a good approach.

Although it is encouraged to reuses the EVM design files, it is important for you to be aware on some of the guidelines to be followed while reusing.  The guidelines are listed:

• Before you start the design, Read through the key collaterals on device product page. The below FAQs provides links to these collaterals:

(+) [FAQ] AM625 Custom board hardware design – Collaterals to Get started - Processors forum - Processors - TI E2E support forums

(+) [FAQ] AM623 Custom board hardware design – Collaterals to Get started - Processors forum - Processors - TI E2E support forums

(+) [FAQ] AM625SIP Custom board hardware design – Collaterals to Get started - Processors forum - Processors - TI E2E support forums

(+) [FAQ] AM625-Q1 or AM620-Q1 Custom board hardware design – Collaterals to Get started - Processors forum - Processors - TI E2E support forums

• Review the available EVMs and Refer to the Right EVM version and revision based on the requirements, application and use case.
• Review the functionality of the sections being reused for completeness. Some of the functionalities could be implemented over multiple pages.
• Review the Change in net names for power supplies and other Signals while optimizing the circuit.
• Review the system level requirements before you remove external protections provided on the EVM Ex: ESD, and diagnostic features including temperature sensors, current monitoring.
• When the schematics is updated and re-sequenced the DNI configurations for all the components in the design will be reset. Make sure the required DNIs are reconfigured in the schematics. This ensures the board functions as expected and also optimizes the BOM cost. It is easier to update the DNIs on the schematics than debugging the board to remove the DNIs.
• Do a self-review or reach out to TI using the E2E forum when alternative design approaches are being considered. Ex: Reset RC connected to the SoC without using debounce circuit.
• It is recommended to perform design rules check for duplicate names, single node nets, off-page connector connections and off-page connector direction.
• Check signal naming and direction of the signals. Signal names and signal direction reduces errors and improves readability.
• heck available design notes on the schematic pages. Add or make update to the design notes as required Ex: Marking of the differential signals, alternative configuration.
• It is recommended to generate the BOM (Bill of Material) early in the design and review the components as per the design requirements.
• Provisioning for JTAG interface would be recommended.
• Provisioning for pullup/pull down resistors for all the bootmode pins that have configuration options is recommended.
• Once the schematics is complete, do a self-review making using of TI collaterals.

Note on EVMs

We do not consider our hardware platforms (EVM) to be a reference design.  They are evaluation platforms and may not represent a proper system implementation.  In many cases, our EVMs are partially or completely designed before we release the processor for fabrication.  This is done so the hardware platform is available when first silicon arrives.  We may learn new device requirements during processor bring-up and bench validation.  If so, these new requirements may not be accounted for in our hardware development platform.  Therefore, TI expects customers to carefully review and follow all requirements defined in the device datasheet, silicon errata, and TRM when designing their system. 

Our hardware development platforms were not designed to be comprehensive of specific system requirements, like radiated emissions, noise susceptibility, thermal management, etc.

EVM vs Data sheet: If you see difference between TI EVM and Data sheet, it is recommended to follow the Data sheet.

Tools version used 

On AM62x SK we use the following software :

Schematic Entry- OrCAD Capture CIS 16.6

PCB Layout - Cadence Allegro 17.4 for REV A version & Cadence Allegro 17.2 for earlier versions