Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
.
Device Selection and features
Product Page
https://www.ti.com/product/AM625
Datasheet
AM62x Sitara
Processors datasheet (Rev. A) (ti.com)
Silicon Errata
AM62x Sitara Errata (Rev. B) (ti.com)
Technical Reference Manual
AM62x Sitara Processors Technical Reference Manual (Rev. A) (ti.com)
Custom Board design
Hardware Design Guide
Hardware Design Guide for AM62x Devices (ti.com)
Evaluation EVM
https://www.ti.com/tool/SK-AM62B-P1
SK-AM62 Evaluation board | TI.com
SysConfig (Pinmux) for SK-AM62 and SK-AM62-P1
SysConfig (Pinmux) for for SK-AM62B
EVM design files in Altium format
CAD symbols
https://www.ti.com/product/AM625#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM625#order-quality
Lead finish/Ball material
SnAgCuBi
Package pad diameter and substrate pad dimension
AM625 -> ALW pkg: ball diameter 0.3mm : substrate pad 0.25mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.
Schematic Review Checklist
AM62x Schematic Review Checklist
DDR Board Design and Layout Guidelines
AM62x DDR Board Design and Layout Guidelines (ti.com)
Target impedance
Impedance target values for VDD_CORE on AM625/AM623
Low freq (< 1MHz) : 22mOhm
Mid freq (1 < 20MHz) : 31 mOhm
High freq (20 < 50 MHz) : 40 mOhm
This is valid for either of the core voltage values. We do not provide target impedance values for other rails on AM62x.
AM62x Maximum Current Ratings
https://www.ti.com/lit/an/sprada6/sprada6.pdf
SoC power solutions Application notes:
Discrete Power Solution for AM625 / AM623
https://www.ti.com.cn/cn/lit/an/sluaak2/sluaak2.pdf
Powering the AM62x with the TPS65219 PMIC
https://www.ti.com/lit/an/slvafd0a/slvafd0a.pdf
Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/an/sprac76f/sprac76f.pdf
Design Simulation files
https://www.ti.com/product/AM625#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/an/spracn9d/spracn9d.pdf
https://hands.com/~lkcl/ddr3/sprabi1a.pdf
https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
SYSCONFIG
DDR subsystem register configuration tool
Technical Documents
Collaterals and app notes
https://www.ti.com/product/AM625#tech-docs
Technical Support
AM625 Custom board design - FAQs
Previous E2E threads - Keywords AM625
Starting a new thread
Useful links
Notes
Regards,
Sreenivasa
Hi Board designers,
Configuring Hysteresis
Data sheet
6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-22. GPIO0 Signal Descriptions
Table 6-23. GPIO1 Signal Descriptions
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10.2 MCU Domain
Table 6-24. MCU_GPIO0 Signal Descriptions
(1) This GPIO input signal has
TRM
5.1.1.3.1.1 Pad Configuration Registers
The pad configuration registers are used to configure most of the device pads. Each pad configuration register
(PADMMR_PADCONFIG0 to PADMMR_PADCONFIG181) is assotiated only with one pad and has bits as
described in Table 5-4.
14.2.1.2 Pad Configuration Registers
14.2.1.2.1 Pad Configuration Register Functional Description
This is the AM64x description.
Table 14-6172. Description Of The Pad Configuration Register Bits for AM625 will be updated : Bit13-11
6.1.1.2.1.2 I/O Debounce Control Registers
Table 6-1. Debounce Period Values
This table needs to be updated.
Refer AM64x table
Regards,
Sreenivasa
