[FAQ] AM623 Custom board hardware design – Collaterals to Get started

Hi Board designers, 

The below links are a quick reference to the collaterals that can be referred when starting a custom design.

Device Selection and features

Product Page

https://www.ti.com/product/AM623

Note:

Any AM62x device implemented in the ALW package will be pin2pin compliant to all other AM62x devices implemented in the ALW package.

Datasheet

AM62x Sitara Processors datasheet

https://www.ti.com/lit/pdf/sprsp58

Silicon Errata

AM62x Processor Silicon Revision 1.0

https://www.ti.com/lit/pdf/sprz487

Technical Reference Manual

AM62x Sitara Processors Technical Reference Manual

https://www.ti.com/lit/pdf/spruiv7

Technical Reference Manual W/o registers 

spruiv7b noRegisters.pdf

Custom Board design:

Hardware Design Considerations

Hardware Design Considerations for Custom Board Using AM625, AM623, AM625SIP, AM625-Q1, AM620-Q1 Family of Processors

https://www.ti.com/lit/pdf/sprad05

Schematic Design and Review Checklist

AM62x Processor Family (Recommended)

AM623, AM625, AM625SIP, AM620-Q1, AM625-Q1 Processor Family Schematic Design Guidelines and Schematic Review Checklist

https://www.ti.com/lit/pdf/sprado3

AM62X processor families (For references) 

AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Families Schematic, Design Guidelines and Review Checklist

https://www.ti.com/lit/pdf/sprad21

Power Consumption

AM62x Maximum Current Ratings

https://www.ti.com/lit/pdf/sprada6

Enabling Low Power Embedded Systems With AM62x Processors
www.ti.com/.../sprad41.pdf
AM62x Power Consumption
www.ti.com/.../spradg1.pdf

AM62x Power Estimation Tool

https://www.ti.com/lit/pdf/sprad31

AM62x Power Consumption

https://www.ti.com/lit/pdf/spradg1

SoC power solutions Application notes:

Discrete Power Solution for AM62x

https://www.ti.com/lit/pdf/sluaak2

Powering the AM62x with the TPS65219 PMIC

https://www.ti.com/lit/pdf/slvafd0

Evaluation - EVM

SK-AM62B-P1 Design Package Content Overview (Rev. A)
www.ti.com/.../SK-AM62B-P1
www.ti.com/.../sprt777
Design File Package
www.ti.com/.../spar001

SK-AM62-LP Design Package Content Overview
www.ti.com/.../SK-AM62-LP
www.ti.com/.../sprt778
Design File Package
https://www.ti.com/lit/zip/sprr471

SK-AM62B Design Package Folder and Files List
www.ti.com/.../SK-AM62B
www.ti.com/.../sprt784
Design File Package
www.ti.com/.../sprr481

AM62x starter kit for Sitara processors
www.ti.com/.../SK-AM62
Design File Package
https://www.ti.com/lit/zip/sprr448

SK-AM62  SysConfig (Pinmux)

1374.am62x_sk.zip

 EVM files in Altium format 

8738.AM62x_E3_Altium.zip

EVM schematics 16.2 

PROC114E3_SCH_16_2.zip

PROC114E3A_SCH_16_2.zip

Schematics (Reference) for RMII interface 

PROC135E1_SCH.pdf

PROC156E1_SCH.pdf

RMII_Length_Matching.xlsx

Note:  We did functionally validate the common clock configuration. No other clocking options were tested.

Ethernet PHY daughter card 
https://www.ti.com/tool/DP83867-EVM-AM

https://www.ti.com/tool/DP83826-EVM-AM2

https://www.ti.com/tool/TIDA-00928

Nand daughter board info for reference (GPMC)

2804.proc143e2_sch.pdf

PROC143E1_GPMC NAND for SK-AM62-LP.zip

GPMC NAND Expansion Card 

HSE NAND EXP BOARD + BREAKOUT BOARD.zip

There seems to be a muxed GPMC interface implemented.
https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/TMDXICE3359_SCH.pdf

CAD symbols

CAD symbol specific to the selected device can be chosen from the device product page. Refer below:

https://www.ti.com/product/AM623#cad-cae-symbols

Ordering & quality

https://www.ti.com/product/AM623#order-quality

Package pad diameter and substrate pad dimension 

AM623 -> ALW pkg:   ball diameter 0.3mm : substrate pad 0.25mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.

Section and Document reference:

. Width/Spacing Proposal for Escapes

https://www.ti.com/lit/an/sprad13a/sprad13a.pdf

The recommendation is to use 0.25mm (10 mil) BGA landing pads to meet the requirements

Lead finish/Ball material

SnAgCuBi  

(+) AM623: BGA structure diagram data request - Processors forum - Processors - TI E2E support forums

Copper pad diameter(mm) = 0.3mm

Copper pad thickness(mm) = 0.016mm

Solder mask opening diameter(mm) = 0.25mm

Solder mask thickness(mm) = 0.015mm

DDR Board Design and Layout Guidelines

AM62x, AM62Lx DDR Board Design and Layout Guidelines

https://www.ti.com/lit/pdf/sprad06

Escape Routing for PCB Design

AM62 Escape Routing for PCB Design

https://www.ti.com/lit/pdf/sprad13

Design Simulation files

https://www.ti.com/product/AM623#design-tools-simulation

Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)

AM62x PDN Target impedance values:

Impedance target values for VDD_CORE on AM625/AM623

Low freq (< 1MHz) : 22mOhm

Mid freq (1 < 20MHz) : 31 mOhm

High freq (20 < 50 MHz) : 40 mOhm

This is valid for either of the core voltages (0.75V, 0.85V) and packages. We do not provide target impedance values for other rails on AM62x.

For frequencies above 50 MHz the board decoupling caps do not play a critical role. SoC and Package decaps (if any) will be dominant beyond 50 MHz

Note:

We do not include Buck output inductance in PDN simulations.

For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62x, AM62Lx DDR Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.

To test PDN analysis SoC and LPDDR4 power line, Customer needs the spec of impedance of SoC/LPDDR4 power line. Could you confirm the impedance? 

Here is the plot for the AM62x EVM. However please note that this is an impedance plot of the TI EVM. It should not be used for signoff. The full LPDDR4 system-level simulations must still be run for signoff as prescribed in the LPDDR design guidelines app note.

We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.

Power Distribution Networks: Implementation and Analysis

Sitara Processor Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

Note: The decoupling capacitor numbers and type on the SK/EVM are only intended to serve as a guideline for customers. The true pass/fail criteria is the target impedance published in the PDN app note.

High Speed Board design and Signal integrity simulation 

https://www.ti.com/lit/pdf/spraar7

https://www.ti.com/lit/pdf/spracn9

https://www.ti.com/lit/pdf/sprabi1

SYSCONFIG

DDR subsystem register configuration tool

interactive and intuitive graphical tool for enabling, configuring and generating initialization code for device pin multiplexing 

Technical Documents        

Collaterals and application notes

https://www.ti.com/product/AM623#tech-docs

Technical Support

AM623 Custom board design - FAQs

Previous E2E threads - Keywords AM623

Starting a new thread

(2) TI E2E support forums

Useful links

Sitara family of processors FAQ master list 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1395812/faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families

Other FAQs

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332316/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-p1-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337851/faq-am625-q1-am620-q1-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-lp-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1357533/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1347063/faq-am625sip---custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-sip-schematics

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1114327/faq-what-is-the-difference-between-rmii-slave-signaling-and-rmii-master-signaling

SOC POH
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1492996/am620-q1-the-definition-of-power-of-hour-for-automotive-grade/5736233#5736233

Notes

1. Always ensure you are using the latest version of the documentation.
2. Check the product folder regularly for the latest version.
3. On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
4. If you have any queries or need clarification, use E2E to find similar queries or ask a new question

Regards,

Sreenivasa

Hi Board designers, 

Refer below information  regarding   Package's PAD/SMO information needed

e2e.ti.com/.../faq-am625-package-parameter-description
e2e.ti.com/.../faq-am623-package-s-pad-smo-information-needed
https://e2e.ti.com/support/processors-group/processors---internal/f/processors---internal-forum/1302507/faq-am623-package-alw-contact-pressure-specification-for-thermopad

Inputs regarding maximum clamping force:

we have more updated guidance based on modelling that gives more resolution to pitch. Please see below:

• 0.65mmp/0.8mmp (like ALV)  19 g/solder ball
o 441/ALV  441 x 19g = 8379g

• 0.5mmp (like ALX)  13 g/solder ball
o 293/ALX  293 x 13g = 3809g

General Guidelines:

(+) AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Could you tell them the maximum allowable value of pressure to the top of package ?
Do you have any document for design guide of heatsink and Thermal Interface Material ?

AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV)

This is in our FCBGA app note (pg 52). It looks like TI’s recommendation is 0.015 lbf per BGA ball.

 That same section has some details regarding heat sinks, but I’m not seeing anything too specific. Generally, the customer defines which TIM they should use as well as the design of the heat sink, so I think we can only give them pretty generic guidance.

The diagonals of some of these heat sinks can be designed with extensions to allow direct connection to the board. Back plates can reduce the bending
stress on the board. TI recommends keeping the compressive loading by a heat sink or other attachment below 0.015 lbfper BGA ball.
https://www.ti.com/lit/ug/spru811a/spru811a.pdf#page=52

Regards,

Sreenivasa

Hi Board designers,

Inputs regarding Package shelf life

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1520415/am625-package-shelf-life

Please refer below links

https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html

https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html

https://www.ti.com/packaging/docs/mslsearch.tsp?OPN=AM6254BTGFHIAMCRQ1&searchSelected=devpartno&searchkey=AM625#divline

https://www.ti.com/support-quality/reliability/reliability-home.html

https://www.ti.com/lit/an/spraby1a/spraby1a.pdf

https://www.ti.com/lit/pdf/snoa550

https://www.ti.com/lit/an/slva840/slva840.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf

(+) AM62P: Air Humidity for Storage and Operation - Processors forum - Processors - TI E2E support forums

I got the ask from a customer if we define the storage air humidity and the air humidity in operation for the AM62P? 

I guess not, but I wanted to doublechekc with you. 

Also, this is the requirements they are asking for: 

• Storage air humidity: 30% to 95% RH
• Air humidity in operation: 30% to 95% RH 

Prior to board assembly but removed from sealed packaging -> device is specified as MSL3, rated for 168hrs exposure at ≤30°C/60%RH ambient conditions without a re-bake being required before board assembly.

We have no spec for operational humidity specification, but device completed and passed relevant qualification at MSL3 moisture precondition + 1000hrs 85°C/85%RH THB (Temperature, Humidity, Bias) per standard JEDEC test conditions

Regards,

Sreenivasa

Hi Board designers,

Inputs regarding weight and material content

https://www.ti.com/materialcontent/home

Regards,

Sreenivasa

Hi Board designers,

Inputs related to SR1.1

The Q1 GPN will support SR1.1. SR1.1 is only released on Q1 parts. AM625 and Am623 currently do not have a SR1.1 silicon
Help me underst way for customer to know the GPNs that support SR1.1, is this mentioned somewhere?
Not at a GPN level. The orderable addendum at the end of the datasheet will list this at an OPN level and then each GPN product page will similarly list supported OPNs for that one GPN

Regards,

Sreenivasa

Hi Board designers,

Inputs related to antenna trace impedance:

(+) SK-AM62: Impedance value of Wi-Fi and BLE antenna trace on SK-AM62 board - Processors forum - Processors - TI E2E support forums

I quickly simulated the trace impedance of the antenna traces, and they are all exactly 50 ohms.

In the table you shared, 2^nd to last row shows we could have achieved 50 ohms with reference to L2 GND using 5.8 mil trace width, but because we chose 0402 components the trace width would have been more narrow than the component pads leading to impedance mismatch between trace and the 0402 component pads.

So we widened the traces and used “skip ground” giving more distance to GND on L3 to increase impedance of a wider trace – because wider trace width reduces impedance.

 The trace impedance does jump to 120 ohms right at the antenna due to GND cutouts, but the layout is following the datasheet layout guidelines for that connection.

Regards,

Sreenivasa

Hi Board designers,

Inputs related to device marking

(+) TMS320C6414T: TMS320C6414TBGLZA6 marking confirmation - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa