TDA4VM: How to calculate pclk properly.

hi,

That's strange. Above equation is correct for calculating pixel clock..  What is the sysclock/reference clock you are using on this board? Can you please refer to below FAQ in case you are using different sysclk.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1185013/faq-tda4vm-how-to-change-edp-driver-for-the-different-sysclk0-input

Regards,

Brijesh

Hi,

I checked SW and HW that are set as 19.2MHz.

Does display device affect?

Thank you. 

Hi youngwoo lee,

Are you sure that this is correct resolution and its parameters?

Because in SDK, by default, we use 1080p @60fps output and for this resolution, we are setting 148.5MHz pixel clock, which is correct as per the resolution information. This works fine on multiple displays.. 

Regards,

Brijesh

Hi,

Our Customer requires 3200 x 720, 30fps.

So I changed some configuration.

I want to know how to check DP link training is correct.

Thank you. 

Hi,

If the link training fails, it will not continue and we will not get any display.. So it looks like link training is successful. It would be called in appDctrlDpHpdCbFxn APi in vision_apps\utils\dss\src\app_dctrl.c file..

Can you please confirm that you are using latest release SDK08.05 for testing it out?

Regards,

Brijesh