AM625: OLDI0_CLK0P/N no output

Hi Tony,

Is it possible for your customer to use the latest PSDK (8.05)? We have made changes to the LVDS driver and my recommendation would be to use the latest tree.

Regards,
Krunal

Krunal,

There is OLDI0_CLK0 output with same Kernel and DT run on AM62x-SK,  can we excluding software configuration? 

Anyway, I let customer trying PSDK8.05.

Hi Tony,

One thing to check would be the OLDI PD Control Register: 0x00108700. If bit 0 and bit 1 are set high then it means the OLDI is turned off. Also, please review the following "Steps to stabilize OLDI signal output from AM625 SoC:" in the docs: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_05_00_21/exports/docs/linux/How_to_Guides/Target/How_to_enable_Microtips_LVDS_Panel_on_AM62_SK_EVM.html?highlight=lvds . 

Regards,
Krunal

Krunal,

From customer board, the bandgap is power down as below. is it related to LVDS panel? or driver bug?

root@am62xx-evm:~# devmem2 0x00108700
/dev/mem opened.
Memory mapped at address 0xffff97ee4000.
Read at address  0x00108700 (0xffff97ee4700): 0x00000102

After clear the bandgap bit. LVDS Clock output rightly now, and timing is right.

But only display a static image, not update as that on DPI. Now still work on PSDK8.04, not sure whether it is problem of the SDK. 

Need sometime to migrate to PSDK8.05.

The bandgap power down is not fixed in PSDK8.5 yet? will update in PSDK8.6?

Now the LVDS works fine.

I add the diff patch for PSDK8.5

5700.psdk8-5-tidss.patcth

Krunal,

Customer would like to know the root cause:

#1. From the description on on-line user guide, sounds like the issue related to specific panels?

Steps to stabilize OLDI signal output from AM625 SoC:

During internal tests, certain LVDS panels showed distorted output or had no output on the screen. The issue was related to the bandgap register and the below steps show how to resolve the issue:

#2. But on AM62-sk, even did not connect LVDS panel, with same configuration as that of customer board, still can probe LVDS clock, but on customer board, connect panel or not, no LVDS clock output, so seems not related to panel. 

If it is panel specific, how can panel impact the Power bit setting on SOC side?

peaves said:

The band gap reference sets the common mode voltage for the LVDS outputs.

Seems Band gap reference is a internal signal, I did not find it in TRM.

What impact the band gap reference? Does the band gap reference varies on difference AM62x device or difference AM62x based PCBA?