I'm migrating to the latest SDK 08.02 and having boot issues with several peripheral devices that work using SDK 05.00. The DTS for am335x-evm.dts has changes in several areas and I'm wondering if I should be following the 08.02 dts more closely. For example, the evm ethernet related devices were:
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid";
}; and are now
&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rgmii-id";
ti,dual-emac-pvid = <1>;
};
specifically, the changes in MDIO and CPSW. My DTS models the original form and ethernet (as well as other devices) no longer comes up during boot.
Below are dmesg log excerpts from my SDK 05 boot vs SDK 08 boot
SDK05:
[ 0.998552] console [ttyS0] enabled [ 1.004252] omap_rng 48310000.rng: Random Number Generator ver. 20 [ 1.010682] random: fast init done [ 1.014214] random: crng init done [ 1.032161] brd: module loaded [ 1.043960] loop: module loaded [ 1.051422] spi_omap2_mcspi: DMA requested (rx0, 41, 0). [ 1.057000] spi_omap2_mcspi: DMA requested (tx0, 40, 0). [ 1.077338] spi spi0.0: spi_omap2_mcspi_slave: DMA RX requested (rx0, 17). [ 1.084279] spi spi0.0: setup: wl 8, speed 32000000, sample CPHA edge, clk no CPOL [ 1.091964] spi-omap2-mcspi-slave: Enabling slave dma (0) [ 1.099077] mdio_bus fixed-0: GPIO lookup for consumer reset [ 1.099093] mdio_bus fixed-0: using lookup tables for GPIO lookup [ 1.099105] mdio_bus fixed-0: lookup for GPIO reset failed [ 1.099134] libphy: Fixed MDIO Bus: probed [ 1.120319] mdio_bus 4a101000.mdio: GPIO lookup for consumer reset [ 1.120337] mdio_bus 4a101000.mdio: using lookup tables for GPIO lookup [ 1.120347] mdio_bus 4a101000.mdio: lookup for GPIO reset failed [ 1.174932] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000 [ 1.182645] davinci_mdio 4a101000.mdio: detected phy mask fffffffe [ 1.190278] Micrel KSZ8081 or KSZ8091 4a101000.mdio:00: micrel using 50 mhz external clock [ 1.198795] libphy: 4a101000.mdio: probed [ 1.202836] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Micrel KSZ8081 or KSZ8091 [ 1.213623] cpsw 4a100000.ethernet: Detected MACID = 6c:c3:74:9e:99:b5 [ 1.220534] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4 [ 1.227006] cpsw 4a100000.ethernet: ALE Table size 1024 [ 1.232314] cpsw 4a100000.ethernet: cpts: overflow check period 500 (jiffies) [ 1.241561] i2c /dev entries driver [...] [ 12.427209] net eth0: initializing cpsw version 1.12 (0) [ 12.599439] Micrel KSZ8081 or KSZ8091 4a101000.mdio:00: attached PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL) [ 12.945363] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 14.806612] cpsw 4a100000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 14.838352] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes readySDK08:
[ 2.530186] printk: console [ttyS0] enabled [ 2.538524] omap_rng 48310000.rng: Random Number Generator ver. 20 [ 2.545128] random: crng init done [ 2.564976] brd: module loaded [ 2.578002] loop: module loaded [ 2.602377] mdio_bus fixed-0: GPIO lookup for consumer reset [ 2.602404] mdio_bus fixed-0: using lookup tables for GPIO lookup [ 2.602417] mdio_bus fixed-0: No GPIO consumer reset found [ 2.612022] mdio_bus 4a101000.mdio: GPIO lookup for consumer reset [ 2.612048] mdio_bus 4a101000.mdio: using device tree for GPIO lookup [ 2.612101] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0/mdio@1000[0]' [ 2.612139] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0/mdio@1000[0]' [ 2.612159] mdio_bus 4a101000.mdio: using lookup tables for GPIO lookup [ 2.612172] mdio_bus 4a101000.mdio: No GPIO consumer reset found [ 2.672277] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000 [ 2.679992] davinci_mdio 4a101000.mdio: detected phy mask fffffffe [ 2.687578] mdio_bus 4a101000.mdio:00: GPIO lookup for consumer reset [ 2.687598] mdio_bus 4a101000.mdio:00: using lookup tables for GPIO lookup [ 2.687611] mdio_bus 4a101000.mdio:00: No GPIO consumer reset found [ 2.688386] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Micrel KSZ8081 or KSZ8091 [ 2.699189] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4 [ 2.705756] cpsw 4a100000.ethernet: ALE Table size 1024 [ 2.711162] cpsw 4a100000.ethernet: cpts: overflow check period 500 (jiffies) [ 2.718527] cpsw 4a100000.ethernet: Detected MACID = 6c:c3:74:9e:99:b5 [ 2.727949] i2c /dev entries driver [...] [ 12.492584] cpsw 4a100000.ethernet: initializing cpsw version 1.12 (0) [ 12.738677] Micrel KSZ8081 or KSZ8091 4a101000.mdio:00: attached PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
My DTS is below:
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x Catawba";
compatible = "ti,am335x-catawba", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x08000000>; /* 128 MB */
};
chosen {
stdout-path = &uart0;
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&gpio_pins>;
gpio_pins: pinmux_gpio_pins {
pinctrl-single,pins = <
/* gpiochip0: GPIOs 0-31 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7) /* gpo1 (V15) gpmc_ad8.gpio0[22]) */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7) /* gpo0 (W16) gpmc_ad9.gpio0[23]) */
AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7) /* gpi0 (T12) gpmc_ad10.gpio0[26]) */
AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7) /* gpi1 (U12) gpmc_ad11.gpio0[27]) */
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE7) /* PMIC_INT (R15) gpmc_wait0.gpio0[30]) */
AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* POE_T2P (W18) gpmc_wpn.gpio0[31]) */
/* gpiochip1: GPIOs 32-63 */
AM33XX_IOPAD(0x800, PIN_OUTPUT | MUX_MODE7) /* mcu_dsp_rst_ctl (W10) gpmc_ad0.gpio1[0]) */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE7) /* mcu_dsp_not_resetn (V9) gpmc_ad1.gpio1[1]) */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE7) /* mcu_handshake1 (V12) gpmc_ad2.gpio1[2]) */
AM33XX_IOPAD(0x80C, PIN_INPUT | MUX_MODE7) /* mcu_handshake2 (W13) gpmc_ad3.gpio1[3]) */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE7) /* mcu_handshake3 (V13) gpmc_ad4.gpio1[4]) */
AM33XX_IOPAD(0x814, PIN_OUTPUT | MUX_MODE7) /* mcu_handshake4 (W14) gpmc_ad5.gpio1[5]) */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE7) /* mcu_handshake5 (U14) gpmc_ad6.gpio1[6]) */
AM33XX_IOPAD(0x81C, PIN_INPUT | MUX_MODE7) /* mcu_handshake6 (W15) gpmc_ad7.gpio1[7]) */
AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE7) /* mcu_hwait (U13) gpmc_ad12.gpio1[12]) */
AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE7) /* timer_sync (T13) gpmc_ad13.gpio1[13]) */
AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE7) /* am3351_tp0 (W17) gpmc_ad14.gpio1[14]) */
AM33XX_IOPAD(0x83C, PIN_INPUT | MUX_MODE7) /* am3351_tp1 (V17) gpmc_ad15.gpio1[15]) */
AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE7) /* nPFO (V18) gpmc_be1n.gpio1[28]) */
AM33XX_IOPAD(0x87C, PIN_OUTPUT | MUX_MODE7) /* mcu_led_pwr_green (W8) gpmc_csn0.gpio1[29]) */
AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* mcu_led_status_red (V14) gpmc_csn1.gpio1[30]) */
AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE7) /* mcu_led_status_green (U15) gpmc_csn2.gpio1[31]) */
/* gpiochip2: GPIOs 64-95 */
AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7) /* mcu_led_rj45_green (U17) gpmc_csn3.gpio2[0]) */
AM33XX_IOPAD(0x88C, PIN_OUTPUT | MUX_MODE7) /* mcu_led_pwr_red (V16) gpmc_clk.gpio2[1]) */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* xcvr_en (V10) gpmc_advn_ale.gpio2[2]) */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* mcu_led_rj45_yellow (U8) gpmc_wen.gpio2[4]) */
AM33XX_IOPAD(0x89C, PIN_INPUT | MUX_MODE7) /* config_reset (V8) gpmc_be0n_cle.gpio2[5]) */
/* gpiochip3: GPIOs 96-127 */
AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE7) /* ethernet interrupt (L19) gmii1_rxdv.gpio3[4]) */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C18) i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (B19) i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT | MUX_MODE0) /* (E19) uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* (F17) uart0_txd.uart0_txd */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x90c, PIN_INPUT | MUX_MODE1) /* (J18) gmii1_crs.rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE1) /* (K19) gmii1_rxer.rmii1_rxer */
AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* (K17) gmii1_txen.rmii1_txen */
AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* (L18) gmii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* (M18) gmii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE1) /* (P18) gmii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE1) /* (P19) gmii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x944, PIN_INPUT | MUX_MODE0) /* (K18) rmii1_refclk.rmii1_refclk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x928, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* (P17) mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* (R19) mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT| MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT| MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* (G19) mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* (G17) mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* (G18) mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* (H17) mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* (H18) mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* (H19) mmc0_dat3.mmc0_dat3 */
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE4) /* (E18) eCAP0_in_PWM0_out.spi1_sclk */
AM33XX_IOPAD(0x968, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE4) /* (F19) uart0_ctsn.spi1_d0 MISO */
AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE4) /* (F18) uart0_rtsn.spi1_d1 MOSI */
AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE4) /* (E17) uart1_ctsn.spi1_cs0 */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* (A18) spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* (B18) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* (B17) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* (A17) spi0_cs0.spi0_cs0 */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <100000>;
tps@24 {
compatible = "ti,tps65218";
reg = <0x24>;
interrupts = <0 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-controller;
#interrupt-cells = <2>;
dcdc1: regulator-dcdc1 {
/* VDD_CORE limits min of OPP50 and max of OPP100 */
regulator-name = "vdd_core_1";
regulator-min-microvolt = <1078000>;
regulator-max-microvolt = <1122000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2: regulator-dcdc2 {
/* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
regulator-name = "vddint_1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3: regulator-dcdc3 {
regulator-name = "vdd_ddr3_1";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
regulator-state-disk {
regulator-off-in-suspend;
};
};
dcdc4: regulator-dcdc4 {
regulator-name = "d3.3v_1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "cap_vdd_rtc";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
dcdc6: regulator-dcdc6 {
compatible = "ti,tps65218-dcdc6";
regulator-name = "vdds_rtc";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
ldo1: regulator-ldo1 {
regulator-name = "v1_8d";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
interrupt-parent = <&gpio3>; // ethernet interrupt gpio3_4
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
};
&mmc1 {
status = "okay";
vmmc-supply = <&dcdc4>;
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
};
//&rtc {
// clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
// clock-names = "ext-clk", "int-clk";
//};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
system-power-controller;
};
&wkup_m3_ipc {
//ti,scale-data-fw = "am335x-catawba-scale-data.bin";
};
//&sgx {
// status = "okay";
//};
&tscadc {
status = "okay";
adc {
ti,adc-channels = <0 1>;
};
};
&spi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "master,bf548";
reg = <0>;
spi-max-frequency = <16000000>;
spi-cpha;
};
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
ti,pindir-d0-out-d1-in = <1>;
slave@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "slave,bf548";
reg = <0>;
spi-max-frequency = <32000000>;
spi-cpha;
};
};
&cpu0_opp_table {
oppnitro-1000000000 {
opp-supported-hw = <0x06 0x0100>;
};
};
