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Original question:

AM625: Confusion about GPIO of MAIN Domain

AM625: GPIO number

Tony Tang
Mastermind 30542 points

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Similar question as this post, Is there confirmation from design team?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1182650/am625-confusion-about-gpio-of-main-domain

How many Main domain GPIO0 is available on AM625x? On TRM SPRUIV7A, it should be 0-86, 

but on datasheet and sysconfig tool,  GPIO0_87 to GPIO0_91 are available. 

There are many description in TRM shows above GPIOi_87 are not available.

I think these description copy from AM64x TRM, as on AM64x device, there are really only GPIO0_0 to GPIO0_86. 

Need Clarification and correction.

  • 0
    TI__Guru**** 224355 points

    Hello Tony, 

    Thank you for the query.

    The GPIO numbers in the datasheet (and sysconfig) are the numbers to be considered.

    Your observation on the GPIO numbers seems correct and the team is working to make the GPIO numbers in the TRM generic.

    I expect these updates to be available in the next version of the TRM.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Mastermind 30542 points

    Sreenivasa,

    Thanks for confirmation of the spec.

    Bin,

    Since AM62x main domain GPIO0 has pin from 0-91, GPIO1 has 0-51, Whether below .dts configuration need to be modified.

    main_gpio0: gpio@600000 {
    compatible = "ti,am64-gpio", "ti,keystone-gpio";
    reg = <0x0 0x00600000 0x0 0x100>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-parent = <&main_gpio_intr>;
    interrupts = <190>, <191>, <192>,
    <193>, <194>, <195>;
    interrupt-controller;
    #interrupt-cells = <2>;
    ti,ngpio = <87>; //change to 92?
    ti,davinci-gpio-unbanked = <0>;
    power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
    clocks = <&k3_clks 77 0>;
    clock-names = "gpio";
    };

    main_gpio1: gpio@601000 {
    compatible = "ti,am64-gpio", "ti,keystone-gpio";
    reg = <0x0 0x00601000 0x0 0x100>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-parent = <&main_gpio_intr>;
    interrupts = <180>, <181>, <182>,
    <183>, <184>, <185>;
    interrupt-controller;
    #interrupt-cells = <2>;
    ti,ngpio = <88>;  //change to 52?
    ti,davinci-gpio-unbanked = <0>;
    power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
    clocks = <&k3_clks 78 0>;
    clock-names = "gpio";

  • 0 in reply to Tony Tang
    TI__Guru**** 179926 points

    Hi Tony,

    Yes, if the numbers in the datasheet are correct, the DTS should be updated as you stated.

    I will work with Sreenivasa and the SW Dev team to address this.

  • 0 in reply to Bin Liu
    TI__Guru**** 224355 points

    Hello Bin, 

    Thank you for the inputs.

    Tony, I am working with the team. As i said the TRM related Jira was filed and updated. I will have to file a jira for the SDK updates.

    Regards,

    Sreenivasa