Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: SYSCONFIG
I modified the example C:\ti\mcu_plus_sdk_am64x_08_03_00_18\examples\drivers\gpio\gpio_input_interrupt to use GPIO1_61 on my own board. I get interrupts as expected in my application when I load through CCS running on core R5_0_0.
I then use this example code in a FreeRTOS application which gets loaded from linux. In this case I don't get interrupts, I instead get an error return from Sciclient_rmIrqSet() of -1. I verified that linux doesn't have any GPIO1 settings in the device tree.
I notice that the example, and thus my R5 code, use the interrupt router CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8. I checked the interrupt router resource setting under linux at [1]. I use the sysconfig tool with am64x-evm.syscfg to examine the int router settings. MAIN_0_R5_0, MAIN_0_R5_2 have no settings. MAIN_0_R5_1, MAIN_0_R5_3 have settings, but the "Main GPIO Interrupt Router Count" is 0, while MAIN_1_R5_1, MAIN_1_R5_3 have the "Main GPIO Interrupt Router Count" set to 2. Core A53_2 has "Main GPIO Interrupt Router Count" set to 12,
I then made my own syscfg file copied from am64x-evm.syscfg and modified the GPIO interrupt routing so that Core A53_2 has "Main GPIO Interrupt Router Count" set to 8, MAIN_0_R5_{0,3} are set to 4, MAIN_1_R5_{1,3} are set to 0.
I then copy the files to the k3-image-gen-2022.01 appropriate directories and rebuild tiboot3.bin. Using this tiboot3.bin should have proper board config for the TISCI software. But I still get the Sciclient_rmIrqSet() error -1.
I also tried using CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_{9,15} in the example board.c, but that made no difference.
How can I get the R5 core to handle GPIO interrupts when runnig in a linux environment?
This interrupt routing is difficult to understand, even after reading the TRM. For instance, there are only two R5_0 cores, what is the meaning of MAIN_0_R5_{2,3}?
[1] ti/ti-processor-sdk-linux-rt-am64xx-evm-08.02.00.23/board-support/k3-respart-tool