AM6412: AM6412 Pinout creation

Alex

I do see the discrepancy that you have highlighted. I suspect the datasheet is correct and the tool should not be showing any GPI(O) options on the AINx pins. I am working to confirm this.

Can you elaborate more ion the GP input only?

--Paul 

Hello,

The main issue that one can miss is that the datasheet , in the main table (6.1) for pin out purposes , won't explicitly mention the dual use of the ADC Pins.

So for example in my case, where I haven't used the ADC pin G20 , and table 6.2 was mentioning only single use :ADC0_AIN0 , I almost missed the fact that this G20 is GPIO 80 , but with Input only use (this is mentioned in table 6.2).

Also Sysconfig tool , wont inform for Input only use at GPIO  80 when ADC function is not selected.

Please confirm that for our pinout we stick to the Sysconfig csv output and table 6.1 from datasheet.

If this is not confirmed , please let us know as this is the most critical step at this phase...(to prepare a correct pinout)

Thanks

Alex

Hello Paul,

Is there any update ?

Thanks

Alex

Alex

Here is the correct information:

1. The ADC AINx pins support the GPI function (not GPIO)
2. AINx pins and muxed GPI pins are mutually exclusive – all AINx or all GPI, no mixing.
3. Data sheet does not list the GPI pins in table 6-1 as no padconfig register exists

The SysConfig tool needs to be updated to reflect the GPI only functionality of the AINx muxed pins, as well as their exclusive nature.

--Paul 

Hello Paul,

Thanks for the update.

I need you to make clear the following please :

1) In my case , where I will be using them as GP input pins , how will these be configured..since there is no Pad_Config register ?  The sysconfig tool , will have them selected as GPIO pins (80 to 87). Is there any special SW handling ?

2) Please verify that table 6.1 of latest available datasheet is the table to use for our pin-out preparation.(CRITICAL)

Thanks

Alex

Alex

ALEXANDROS APOSTOLIDIS said:

1) In my case , where I will be using them as GP input pins , how will these be configured..since there is no Pad_Config register ?  The sysconfig tool , will have them selected as GPIO pins (80 to 87). Is there any special SW handling ?

There are details on the GPI mode in the ADC chapter (12.1.1) of the device TRM, ADC GPI Integration.. The mux option is selected using the CTRLMMR_ADC0_CTRL register which is detailed in section 5.1 of the device TRM. 

ALEXANDROS APOSTOLIDIS said:

2) Please verify that table 6.1 of latest available datasheet is the table to use for our pin-out preparation.(CRITICAL)

I do not see any changes pending that would impact table 6-1 of the datasheet.  However, I will confirm with the internal team. I may not have feedback until early next week. 

--Paul

Hello,

Ok for (1) 

As far as (2) , take your time for this. Most critical on the other hand , is , if using the 6.1 table is the correct way to go preparing the schematic symbol pinout.

Is this what TI suggests for pin-out preparation ? 

Thanks

Alex

I have confirmed that there are no updates to table 6-1 pending at this time. 

You may also be able to use the default symbol as a baseline - https://www.ti.com/product/AM625?keyMatch=AM625&tisearch=search-everything&usecase=GPN#cad-cae-symbols

--Paul