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C6678 Hyperlink Routing Guidelines

Richard Marsh
Intellectual 760 points

Hi,

I have been looking at the Hyperlink routing guidelines in the Hardware Design Guide (sprabi2, Nov2010) - section 4.3.4 MCM Net Classes & Specific Rules. 

 

Qu1:
The guidelines seem confused. They give different matching guidelines for TX pairs (match to 5ps) and RX pairs (match to 1ps).  But when you connect two DSP's together the RX pairs connect to the TX pairs, so you can't have different routing guidelines - they are the same net.

Qu2:
Then when it comes to the LVCMOS sideband signals, e.g. MCMTXFLCLK/MCMTXFLDAT, the routing guidelines say they must also be matched as a pair to 5ps and as a group be within 6ps of the 12.5GHz serial links.  Aren't these slower LVCMOS signals?  Do they really need to be so tightly constrained?

Qu3:
What impedance should the LVCMOS sideband signals be routed at?  They aren't differential are they?

Qu4:
What are the MCMREFCLKOUTP/N signals for? I can find no mention of them anywhere.

 

Of course, this would all be a lot easier if the documentation was updated - the current one was released in Nov.  When can we expect a new version of the Hardware Design Guide?

 

Cheers,

 

Richard

  • 0
    TI__Mastermind 42545 points

    Presently we are working to complete characterization of the silicon and the update to the data manual.  Once this is complete we can shift focus to the rest of the collateral.  I've attached the updated section of the Hyperlink routing guidelines which includes most of the information that you've requested. Specifically your answers are below.

    Qu1: Each differential pair, both transmit and receive, should be skew matched to within 1ps as described in the attached document.

    Qu2: The LVCMOS sideband signals should be matched in pairs, MCMRXFLCLK to MCMRXFLDAT and MCMTXFLCLK to MCMTXFLDAT, to within 250ps as described in the attached document.

    Qu3: The LVCMOS sideband signals are not controlled impedance and are not differential pairs.

    Qu4: The MCMREFCLKOUTP/N signals can be connected to the MCMREFCLKP/N of the second component attached to with Hyperlink.  Although this is included as an option for the designer it should be noted that the jitter characteristics of the MCMREFCLKP/N most be met by both components.  Since some jitter will be added to the clock by the first component this is not the recommended method of distributing the clock.  It is recommended that two outputs from an external clock distribution component which meets the jitter standards for the MCMREFCLKP/N be routed seperately to the MCMREFCLKP/N of each component.

    1805.hyperlink routing rules 6July11.pdf

  • 0 in reply to Bill Taboada
    Intellectual 760 points

     

    Many thanks Bill.

     

    Cheers,

     

    Richard.

  • 0 in reply to Bill Taboada
    Prodigy 80 points

    Hi Bill,

    I am looking at the last SPRABI2B from March 2012.

    In continuation to Richard questions on the HyperLink routing recommendations.

    There is a request to route the Differential pairs as microstrip on external layers - i quote :

    "To prevent crosstalk ina simple board stack-up, we recommend that the

    differential receive pairs be routed as microstrip (outer layer) on one side of the
    board and the differential transmit pairs be routed as microstrip (outer layer) on
    the other side of the board."

    Since the Hyperlink connectivity is between 2 DSP's and  Hyperlink BGA pins are spread in external and internal BGA rows

    and TX is connected to RX.

    If you start routing on external layer top from BGA pins on rows 1 or 2  ( BGA is mounted on TOP ) to connect to the second BGA pins you need to reach pins in row 4 and 5

    Question 1 ) Can you explain how can this accomplished - do you have a Reference design that complies to this request ? 

    Question 2) what do you mean by "simple board stack-up" my boards will be about 18 layers with 9 PWR/GND layers - how is it related to the routing of hyperlink?

    Question 3) In case of routing in internal layer what is the maximum allowed stub of via without backdrilling and without using blind/buried vias

    I found a reference i quote "In high-speed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s." can be found at http://blog.lamsimenterprises.com/

    If this rule of thumb is correct - can i allow a stub of 300/12.5=24mils=0.6mm ?


    Question 4) Impedance control ( PCB manufacturing variations ) on external layers is not as good in internal layers is the hyperlink sensitive to larger impedance variation variations along the transmission line - length can be up to 4" ?


    Question 5) About signal losses:

    is there any loss budget associated with the hyperlink do you recommend using lower loss matrials/high speed materials ?

    In Extrenal layer traces skin effect problem is greater relative to stripline since of the fact that current preffers flowing adjacent to a reference plane

    stripline has 2 reference planes while microstrip has only one?


    Question 6) you recommend using a GND via near each location the hyperlink changes layer

    Regarding the loss due to impedance discontinuity :

    vias characteristic impedance is lower than 50 ohm - do you recommend trying to increase/control the via impedance ?


    Question 7 ) for ease of routing :i understand that all 4 lanes diff pairs can be swapped ( maintanig pairing) and also each pair can be swapped between P an N


    Cheers,

    Roby