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Original question:

AM4376: DDR3 prime bit swapping

AM4376: About DDR3 Data line swapping

user1201164
Expert 1770 points
Part Number: AM4376
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I would like to confirm something about swapping DDR3 data lines on AM43xx.
Initially, I had seen the post "AM4376: AM4376BZDND80" and thought that it should not swap about prime bits. However, "AM4376: DDR3 prime bit swapping" says that it is possible to swap within byte lane including prime bits.
I think the latter is more correct in terms of the timeline in which it was written, but I am a little concerned because of posts such as under investigation.
Please let me confirm that it is possible to swap within byte lane including prime bits in data lines even when DDR3 is connected with AM43xx as a fly-by.

Best Regards,

Kouji Nishigata

  • +1
    TI__Guru 74610 points

    Kouji, yes the restriction on the prime bit  is not necessary when swapping bits within a byte.  DQ0 prime bit can be swapped along with other bits in the byte.  

    Regards,

    James

  • 0 in reply to JJD
    Expert 1770 points

    Hi,JJD

    Thanks for the response.
    Our customer appreciated it.

    May I ask you to check on the other sitara series while you are at it?
    Please let me know if it is better to start a separate question for each.

    AM335x: DDR3/DDR3L
    Swappable in byte lane. Because it does not support hardware write leveling.

    AM47xx: LPDDR2/DDR3/DDR3L
    Swappable in byte lane. Because the response of DQ0 bit required for hardware write leveling is ORed with other DQx bits in the PHY.

    AM57xx: DDR3/DDR3L
    Swappable in byte lane. Because it is supported (support details are unknown).

    AM62xx: LPDDR4/DDR4
    DDR4: Swapable in byte lane if CRC is not used.
    LPDDR4: Swapping is not possible.

    AM64xx: LPDDR4/DDR4
    DDR4: Swapping is allowed in byte lane when CRC is not used. However, prime bits cannot be swapped.
    LPDDR4: Swapping is not allowed.

    For AM62xx/AM64xx, the respective DDR Board Design and Layout Guidelines are helpful. However, there is a subtle difference here. Is this information correct? Is this correct or is there some kind of countermeasure in Sitara?

    Best Regards,

    Kouji Nishigata

  • 0 in reply to user1201164
    Expert 1770 points

    Sorry.

    The last sentence was missing.

    ----------------------------------------------------------------------------------------------------

    Also, some documents on the DDR4 side say that DQ[0..7] is not swappable because it accesses registers in the DDR.
    Is there some countermeasure in Sitara?

    Best Regards,

    Kouji Nishigata

  • +1 in reply to user1201164
    TI__Guru 74610 points

    Kouji, 

    AM335x: similar to AM437x, DQ swizzle is allowed within a byte lane for DDR3/3L designs (cannot swizzle DQS or DM).  Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group).  It is true that AM335x does not support hardware leveling, the leveling is performed using a software algorithm.

    AM437x: DQx swizzle is allowed within a byte lane for DDR3/3L designs (cannot swizzle DQS or DM) as discussed previously.  Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group).

    AM57x: similar to AM335x/AM437x, DQx swizzle is allowed within a byte lane for DDR3/3L designs (cannot swizzle DQS or DM). Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group).

    AM62x:

    DDR4: DQx swizzle is allowed within a byte lane (cannot swizzle DQS or DM).  Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group).  This does not require software configuration changes

    LPDDR4: DQx swizzle is allowed with a byte lane (cannot swizzle DQS or DM), as well as byte lane swapping within a channel.  The AM62x DDR layout guidelines appnote is currently being updated to reflect this.  This requires a DDR register configuration change which is now supported in the sysconfig DDR register configuration tool v9.08

    AM64x:

    DDR4: DQx swizzle is allowed within a byte lane (cannot swap DQS or DM).  Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group).  This does not require software configuration changes.

    LPDDR4: no DQx swizzling or byte lane swapping allowed

    Note that the info above is current, but may change (especially for newer devices), so you should consult the latest DDR layout guidelines appnotes for the specific device.

    Which documents say DDR4 DQx cannot be swizzled?  My understanding is that DDR4 has a special MPR mode for reading MR registers, but this is not used in normal operation. If it is used, then certainly the swizzling of the data bits would have to be taken into account, but even then, there is a serial transfer mode which can be used to overcome this.  

    Regards,

    James

    Regards,

    James

  • 0 in reply to JJD
    Expert 1770 points

    Hi, JJD

    Thanks for the answer.
    Basically, DQ swizzle in a byte lane is possible except for DQS or DM. Also, byte lane itself can be swapped together as a group.
    However, I understood that DQ swizzle is currently not possible only for AM64xx LPDDR4. I will pay attention to the respective "DDR Board Design and Layout Guidelines" for AM62x and AM64xx. (Can I assume that the published Guidelines will be updated soon?)

    > Which documents say DDR4 DQx cannot be swizzled?
    I think this was determined by looking at the website, which probably refers to the JEDEC text, not the TI documents.
    As you pointed out, this is about reading MPR, so I understood that countermeasures are being taken.