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TDA4VM: Enable both PCIE and USB3.0 on SERDES1 simultaneously?

Richard Hu
Intellectual 450 points
Part Number: TDA4VM

Hi, gent:


In our HW design, the M.2 key B connector is connected to both PCIE and USB 3.0 based on SERDES1.(one SERDES lane for PCIE, and the other is for USB 3.0.)
(To support different kinds of 5G LTE module based on PCIE or USB3.0 interfaces.)

The device tree content is as follows

&usb_serdes_mux {
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};

&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_USB3_1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_PCIE3_LANE0>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_QSGMII_LANE5>, <J721E_SERDES4_LANE1_QSGMII_LANE6>,
<J721E_SERDES4_LANE2_QSGMII_LANE7>, <J721E_SERDES4_LANE3_QSGMII_LANE8>;
};
&serdes1 {
//assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
//assigned-clock-parents = <&wiz1_pll1_refclk>;

serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz1 1>;
status="disabled";
};

serdes1_usb_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz1 2>;
};
};

And we aware if we only put "serdes1_usb_link" in serdes1 node, USB 3.0 can work unless we disable "assigned-clocks" and "assigned-clock-parents" in SERDES1 device node as above.

After we put "serdes1_pcie_link" in serdes1 node, USB 3.0 has problem, it keeps showing error message as below:

usb usb2-port1: Cannot enable. Maybe the USB cable is bad?


It looks PCIE affects the USB3.0 signal in SERDES1 internally.

We saw there is a post to discuss the coexistence of PCIE and USB3.0 on SERDES1 as the link below.

TI FAE mentions it can't be achieved in software point of view. But this reply was 3 years ago.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/927119/tda4vm-does-serdes1-support-one-pcie-and-one-usb3-simultaneously

We are wondering how are things going in TI SDK_08_05_00_08.
Is it solved? or it still has software limitation in SDK_08_05_00_08 to enable both PCIE and USB3.0 on SERDES1?


BR,


Richard