CCSTUDIO: Code Composer Studio forum

Wenzhi Hu

Part Number: CCSTUDIO
Other Parts Discussed in Thread: TDA4VH

Hello everyone,

I am trying to use CCS(Code Composer Studio) debug on J784S4 TDA4VH as per below link guide. When loadJSFile("/home/user/ti-processor-sdk-rtos-j784s4-evm-08_06_00_14/pdk_j784s4_08_06_00_31/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j784s4/launch.js"), CCS is always stuck as the below screen and can't move forward.

Meanwhile the XDS110 JTAG connector indicator changes from green to red.

CCS scripting Console log and Console log are attached as below. Could you help me? Thanks a lot

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/08_06_00_14/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j784s4.html#debugging-without-hlos-running-on-a72-rtos-only-baremetal

Fullscreen scriptingConsole.txt Download

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js:> loadJSFile("/home/huwenzhi/workspace/tda4VH_J784S4/ti-processor-sdk-rtos-j784s4-evm-08_06_00_14/pdk_j784s4_08_06_00_31/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j784s4/launch.js")
Connecting to Cortex_M4F_0!
Fill R5F ATCM memory...
Writing While(1) for R5F
Loading DMSC Firmware ... /home/huwenzhi/workspace/tda4VH_J784S4/ti-processor-sdk-rtos-j784s4-evm-08_06_00_14/pdk_j784s4_08_06_00_31/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j784s4-gp.bin
DMSC Firmware Load Done...
DMSC Firmware run starting now...
J784S4 Running the DDR configuration... Wait till it completes!
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

js:> loadJSFile("/home/huwenzhi/workspace/tda4VH_J784S4/ti-processor-sdk-rtos-j784s4-evm-08_06_00_14/pdk_j784s4_08_06_00_31/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j784s4/launch.js")
Connecting to Cortex_M4F_0!
Fill R5F ATCM memory...
Writing While(1) for R5F
Loading DMSC Firmware ... /home/huwenzhi/workspace/tda4VH_J784S4/ti-processor-sdk-rtos-j784s4-evm-08_06_00_14/pdk_j784s4_08_06_00_31/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j784s4-gp.bin
DMSC Firmware Load Done...
DMSC Firmware run starting now...
J784S4 Running the DDR configuration... Wait till it completes!

Fullscreen log_Console.txt Download

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CORTEX_M4F_0: GEL Output: Configuring ATCM for the R5Fs
CORTEX_M4F_0: GEL Output: ATCM Configured.
CORTEX_M4F_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
CORTEX_M4F_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
CORTEX_M4F_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
CORTEX_M4F_0: GEL Output: It also sets the second address translation region to    [0x6000_0000, 0x4000_0000].
CORTEX_M4F_0: GEL Output: This is consistent with the SoC DV assumptions.
CORTEX_M4F_0: GEL Output: R5F Halt bits set.
CORTEX_M4F_0: GEL Output: Debugging disabled.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: Power Domain: On
CORTEX_M4F_0: GEL Output: Module State: Enable
CORTEX_M4F_0: GEL Output: Programming all PLLs.
CORTEX_M4F_0: GEL Output: Programming Main PLL 0 (Main PLL)
CORTEX_M4F_0: GEL Output: Main PLL 0 (Main PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

CORTEX_M4F_0: GEL Output: Configuring ATCM for the R5Fs
CORTEX_M4F_0: GEL Output: ATCM Configured.
CORTEX_M4F_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
CORTEX_M4F_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
CORTEX_M4F_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
CORTEX_M4F_0: GEL Output: It also sets the second address translation region to    [0x6000_0000, 0x4000_0000].
CORTEX_M4F_0: GEL Output: This is consistent with the SoC DV assumptions.
CORTEX_M4F_0: GEL Output: R5F Halt bits set.
CORTEX_M4F_0: GEL Output: Debugging disabled.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: Power Domain: On
CORTEX_M4F_0: GEL Output: Module State: Enable
CORTEX_M4F_0: GEL Output: Programming all PLLs.
CORTEX_M4F_0: GEL Output: Programming Main PLL 0 (Main PLL)
CORTEX_M4F_0: GEL Output: Main PLL 0 (Main PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 3 (CPSW5X PLL)
CORTEX_M4F_0: GEL Output: Main PLL 3 (CPSW5X PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 5 (Video PLL)
CORTEX_M4F_0: GEL Output: Main PLL 5 (Video PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 6 (GPU PLL)
CORTEX_M4F_0: GEL Output: Main PLL 6 (GPU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 7 (MSMC PLL)
CORTEX_M4F_0: GEL Output: Main PLL 7 (MSMC PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 9 (ARM1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 9 (ARM1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
CORTEX_M4F_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 25 (Vision PLL)
CORTEX_M4F_0: GEL Output: Main PLL 25 (Vision PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: All PLLs programmed.
CORTEX_M4F_0: GEL Output: Powering up all PSC power domains in progress...
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMSC
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DEBUG2DMSC
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_GPIO
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN2WKUPMCU
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_TEST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_DEBUG
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_I3C_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_SPARE_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_TEST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_PBIST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_AUDIO
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_ATL
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MLB
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MOTOR
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MISCIO
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_GPMC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPFE
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPE
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_DEBUG
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CC_TOP_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC8B_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SAUL
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_I3C
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_4
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_5
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EDP_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_9GSS
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_3
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powered up all Main Timers.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_2_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_3_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER0_CORE2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER0_CORE3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER1_CORE2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER1_CORE3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCOM
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUPBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCORE
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_0
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_PBIST
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DECODE_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DECODE_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SDE
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE4
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE5
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE6
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up all PSC power domains done!
CORTEX_M4F_0: GEL Output: MCU R5F Cluster set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 0 set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 1 set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 2 set to split mode.
CORTEX_M4F_0: GEL Output: --->>> ==================================================  <<<---
CORTEX_M4F_0: GEL Output: --->>> Set DDR Interelave Configuration: Enable DDR0 only <<<---
CORTEX_M4F_0: GEL Output: --->>> ====================================================  <<<---
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: --->>> DDR controller programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY Data Slice 3 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY Address Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> Set PHY registers for F1 freq... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PHY programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> NO Set PHY registers for F2 freq...  FI and F2 are set to the same<<<---
CORTEX_M4F_0: GEL Output: --->>> Non-CS Interleave CTL_273 0x000001FF.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Manual modification by Rajesh... Before <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_139 0x000E0A09.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_140 0x07000401.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_148 0x08080000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_227 0x15110000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_277 0x01180101.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_377 0x00010000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_430 0x00000105.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Manual modification by Rajesh... <<<---
CORTEX_M4F_0: GEL Output: --->>> Manual modification by Rajesh... After <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_139 0x000E0A09.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_140 0x07000400.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_148 0x08080000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_227 0x15130000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_277 0x01140101.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_377 0x00010000.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Read Back Manual modification CTL_430 0x00000105.. <<<---
CORTEX_M4F_0: GEL Output: --->>> Disable all trainig for pre-silicon simulation <<<---
CORTEX_M4F_0: GEL Output: --->>> Adjust the latencies for pre-silicon simulation <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> Waiting for first frequency change request ... <<<---

over 3 years ago

0 Stanley Liu over 3 years ago

TI__Guru 50045 points

Are you connecting to TDA4VH TI EVM or your own board?

If you are connecting to your own board, you need to update the DDR configuration for the DDR part on your board.

Regards,
Stanley

0 Wenzhi Hu over 3 years ago in reply to Stanley Liu

Prodigy 100 points

Hello Stanley,

Thanks for your reply. I am connectting J784S4 TDA4VH via XDS110 JTAG. So do i need update the DDR configuration? and how to do it？

and the related information is as below:

1. RTOS SDK version: ti-processor-sdk-rtos-j784s4-evm-08_06_00_14

2. CCS version: CCS12.2.0.00009_linux-x64.tar.gz

3. power input:24v

4. NO BOOT Mode

SW11[1-8] = 1000 1000
SW7[1-8] = 0111 0000

0 Karan Saxena over 3 years ago in reply to Wenzhi Hu

TI__Guru* 77954 points

Sorry for the delay in response. Can you comment of whether this is the TI's EVM Board or is this a J784S4 based custom board?

Regards

Karan

0 Wenzhi Hu over 3 years ago in reply to Karan Saxena

Prodigy 100 points

Hi Karan,

I followed the below link guide, have fixed this problem. mainly use

${CCS_INSTALL_PATH}/ccs_base/emulation/gel/K3J7AHP/J7AHP_SI.gel   or

${CCS_INSTALL_PATH}/ccs_base/emulation/gel/J784S4_TDA4VH/J7AHP.gel

instead of

${CCS_INSTALL_PATH}/ccs_base/emulation/gel/K3J7AHP/J7AHP.gel.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1192902/j784s4-evm/4539271?tisearch=e2e-sitesearch&keymatch=J784S4#4539271

But I meet another problem which I can not set active breapoint. As below screenshot. The breakpoint always show "Remain Halted", Could you help support?
The program cannot stop at the breakpoints.

0 Wenzhi Hu over 3 years ago in reply to Karan Saxena

Prodigy 100 points

It is TI's EVM Board without any hardware circuit change.

0 Karan Saxena over 3 years ago in reply to Wenzhi Hu

TI__Guru* 77954 points

Wenzhi Hu said:

But I meet another problem which I can not set active breapoint. As below screenshot. The breakpoint always show "Remain Halted", Could you help support?
The program cannot stop at the breakpoints.

These breakpoints seem to be not enabled, reason could be that the line of code you are trying to put a breakpoint on is optimized. Can you please build the application in debug mode and see if you are able to put breakpoints. Even in this case with a release (i.e. compiler optimized) build, you should be able to put fair amount of source code debug, can you try going to the disassembly window (on the right side on the screenshot you shared) and try putting breakpoints from there?

Regards

Karan

0 Wenzhi Hu over 3 years ago in reply to Karan Saxena

Prodigy 100 points

Hi expert,

I have tried build in debug mode, then set some breakpoint in different source code and disassembly window. The breakpoints still cannot active.

0 Karan Saxena over 3 years ago in reply to Wenzhi Hu

TI__Guru* 77954 points

Can you please share a small screen capture video to show the process? The breakpoints from the disassembly window should always work irrespective of the compiler optimizations.

Regards

Karan

0 Wenzhi Hu over 3 years ago in reply to Karan Saxena

Prodigy 100 points

Hi Karan expert,

Sorry currently I have one more urgent problem, The problem link is as below. Could you help me? Thanks a lot

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1220043/j784s4xevm-in-ti-processor-sdk-rtos-j784s4-evm-08_06_00_14-source-code-what-is-the-buffer-and-function-interface-to-accept-ethernet-data-via-qpenet-board-mac-port-input

0 Karan Saxena over 3 years ago in reply to Wenzhi Hu

TI__Guru* 77954 points

This seems to be an unrelated thread, another TI engineer would be able to help you on it.

Regards

Karan

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