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6678 Inconsistencies in Clock and PLL Names

Brad Griffis
Guru*** 125430 points

I'm extremely confused due to small inconsistencies in the docs.  Please clarify on these various clocks for me and update the docs accordingly.

In the diagram above there is something called "Core PLL" and it has signals SYSCLKP/N feeding into it through a mux.

There is no signal in the data sheet called SYSCLKP or SYSCLKN, nor is there anything called "Core PLL". 

>> So are SYSCLKP/N intended to be CORECLKP/N?  That's my assumption...

>> Is "Core PLL" actually referring to "Main PLL" as described in the data sheet?

 In the snippet above we see references to SYSCLK and "core PLL" again.  The closest diagram I can find to clarify is this one:

 However, in the above diagram we are use the terminology "CORECLK" and "Main PLL", but I do not even see the mux for CORECLKSEL as described in the previous documentation.  So now I'm wondering if these are even referring to the same thing?

Can someone please clarify on the clock diagrams?

 

  • 0
    TI__Guru*** 125430 points

    Further confusion..  The SYSCLKP/N signals which I assumed to be CORECLKP/N show a frequency input range of 122 .88MHz – 307.2 MHz.  However, the data sheet shows the cycle time for CORECLKP/N as 10-25ns (i.e. 40-100 MHz).  So spec-wise these do not seem to match up...

  • 0
    Expert 1120 points

    The first figure you quoted is from "Hardware Design Guide for KeyStone Devices", means it's general information to all the KeyStone devices, includes C66x and TCI66x.

    In other devices' datasheet like C6670 or TCI6618 you may see this:


    And I think your assumption that "SYSCLKP/N = CORECLKP/N" and "CORE PLL = Main PLL" in the C6678 situation is right.

    C6678 does not have an alternate core clock input, so there is not a CORECLKSEL input.

    Han

  • 0 in reply to haopeng han
    TI__Guru*** 125430 points

    haopeng han said:

    C6678 does not have an alternate core clock input, so there is not a CORECLKSEL input.

    Well, I agree from the perspective that I don't see a pin called ALTCORECLKP or ALTCORECLKN.  However, I see many references to ALTCORECLK throughout the 6678 data sheet.

    haopeng han said:

    The first figure you quoted is from "Hardware Design Guide for KeyStone Devices", means it's general information to all the KeyStone devices, includes C66x and TCI66x.

    In this thread you referenced that same diagram in order to tell me the input range for PASSCLK needed to be in the range of 40-312.5 MHz.  However, it seems like you're saying I cannot use that info since it's generic to all keystone devices.  But that's exactly why I was asking the question to begin with, i.e. I expected clock specs to be in the data sheet and not buried in some app note.

  • 0 in reply to Brad Griffis
    TI__Mastermind 30825 points

    Brad,

    There was some cut and paste errors in the initial data manual that had the ALTCORECLK information in the C6678 data manual, when it's not on the device (coming from C6670 data manual.)

    This is being cleaned up and we're getting close to the updated release of the data manual.

    Note that the Core Clock is the clock source and feeds the main PLL and the SYSCLOCKs are the clocks coming out of the main PLL.  I'm not sure where the top diagram w/ the yellow background came from, but it would help if you list the documents you got these out of.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    TI__Guru*** 125430 points

    Chad Courtney said:
    I'm not sure where the top diagram w/ the yellow background came from, but it would help if you list the documents you got these out of.

    Sorry, it's Figure 4 of Hardware Design Guide for KeyStone Devices (sprabi2).

  • 0 in reply to Brad Griffis
    TI__Mastermind 30825 points

    Brad,

    I tracked it down from the HW Design Guidelines SPRABI2

    This was initially created based on the C6670 device but the intent is to use it across the Keystone architecture for which it is valid.  We'll have to do some cleanup and better referencing back to the Data Manuals as the C6678/4/2/1 devices do not have the Altcoreclock and future Keystone devices will not necessarily have the exact same clocking needs.  It's hard to keep these generic for the entire breadth of devices and will require some more scrubbing but thanks for bringing it to our attention.

    Best Regards,
    Chad

  • 0 in reply to Brad Griffis
    TI__Mastermind 42545 points

    Let me add some historical perspective. The C6670 and the C6678 have enough similarities that a common documentation approach was taken.  The C6670, designed mainly for base station environments, includes the option of either clocking the core and the AIF from a single clock source or separate clock sources.  To remain consistent with the previous generation component, the C6474, these clocks became SYSCLK and ALTCORECLK where the AIF is sourced by SYSCLK and the core is sourced by either SYSCLK or ALTCORECLK.  The names were selected because you either had one clock for the system, ie SYSCLK, or you had an alternative clock for the core, ie ALTCORECLK.  Since the C6678 doesn't have the AIF module this wasn't needed and since you were clocking the core the name was changed to CORECLK. 

    Also note that the 66x Keystone Hardware Design Guide was originally produced for the release of the C6670 with the goal of having a generic hardware design guide for the entire family.  Obviously we didn't completely succeed in capturing the differences correctly.  We're working to correct those issues.

  • 0 in reply to Bill Taboada
    TI__Guru*** 125430 points

    Thanks for all the info.  I think we can close this thread.