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Hi,
Processor SDK Linux for Edge AI 08.04.00
In the neural network detection process, that is, when using MMA in DSP,how to control not to use DDR and L1 L2? How to disable L1 L2 in cache?
Hi Nancy,
In general, we do not recommend customers to go too deeply into the PSDK RTOS related portion of EdgeAI which includes memory architecture, since we try to abstract this portion out. With this in mind, I will share related information that is publicly available - although to reiterate, changing the memory architecture is not recommended as this could be an involved process.
For L1/L2, it seems enabling/disabling comes from default Linux code based on the following E2E: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1053166/tda4vm-how-to-disable-the-l1-l2-cache. Recommendation will be the same as my colleague's: "I would recommend posting this on the Linux ARM mailing list: linux-arm-kernel@lists.infradead.org".
For DDR usage, the memory map can be configured following this documentation: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_06_00_12/exports/docs/psdk_rtos/docs/user_guide/developer_notes_memory_map.html. Customers typically use this when they need to use a different size DDR, or move some code to faster memory for performance optimization.
Is there a particular reason for the customer not wanting to use the DDR, L1, and L2 cache? Are they trying to run baremetal code without the need of DDR?
Regards,
Takuma
Hi,Takuma,
This question was raised by me. There are some particular reasons. I'm trying to run baremetal code without the need of DDR, L1 and L2. But, I don't know how to disable them. For DDR, you provided the RTOS version, I am currently the Linux version, they are the same ? Where is modified to disable DDR ?Can you tell me more, I am not very professional. Thank you.
Regards,
Maiunlei
Hi Maiunlei,
For context, EdgeAI SDK itself is an example of how one can run Linux+RTOS on a multi-core SoC, so it takes components from PSDK Linux (code that runs on the main ARM cortex-A72 Linux core) and PSDK RTOS (code that runs on most other remote cores including C7x) to allow users to run Linux and utilize hardware accelerators. More information about which component comes from which SDK can be found here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-edgeai/TDA4VM/08_06_00/exports/docs/common/sdk_components.html.
If you are starting out, I would recommend taking a look at this C7x training: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-bA0wfI4X2g/06.01.01.12/TI_C7X_DSP_TRAINING_00.05_INTERACTIVE.zip
The training is old, but it gives an idea of how one could flash the C7x and run code. However, the training is written for J721E EVM board instead of SK-TDA4VM board, but do you have a J721E EVM?
Regards,
Takuma