Hi,
I am trying to setup BIST on our system based on J721e by using SDL v1.00 in PDK 0805.
With the provided BIST examples and tests, I found that there are some differences upon BIST implementation between the example and the test.
Within the test folder for pbist and lbist, these two are similar for the sequence board init--> osal init --> run bist tests for all the instances(15 for pbist and 6 for lbist)--> restore.
But in the bist example, three boot stages are defined and the bist tests for all the instances are distributed to these three boot stages. Hence these bist instances are executed following a certain order like mentioned in the SDL guide:
Phase #0:
-
PBIST Negative and positive tests for Main Pulsar 0
-
LBIST test for Main Pulsar 0
Phase #1:
-
PBIST Negative and positive tests for Main Pulsar 1, C7x, C66x, VPAC and DMPAC
-
LBIST test for Main Pulsar 1, C7x, VPAC, DMPAC
Phase #2:
-
PBIST Negative and positive tests for A72, HC, Encoder and Decoder
-
LBIST test for A72
Why is the bist example doing so? Are there any dependencies among the cores/IPs? Can I simply implement the PBIST/LBIST by running all the bist instances one by one just like in the pbist/lbist test sources shown?
In addition, I run pbist for all instances as part of SBL on our system before all other cores can run. All the pbist tests are passed and returned but the system cannot be boot up normally afterwards. After debugging I can see there is bus error reported in the below when setting up MCU2_1(Main domain R5F core1) ATCM:
It seems the operation of setting 0xFF to MCU2_1 ATCM is rejected after the pbist(successfully for MCU2_0). If I skip the pbist for MCU2_0/MCU2_1 and run the other pbist instances, the system can be boot up normally. Any idea why is this happening?
Thanks for your patience.