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TDA4AL-Q1: How can I select between TDA4AL or TDA4VL?

Haeyeon Song
Prodigy 140 points
Part Number: TDA4AL-Q1
Other Parts Discussed in Thread: TDA4VL

Environment.

Hardware:  J721EXCP01EVM + J721S2X SOMG01 EVM(TDA4VL/TDA4AL/TDA4VE)

Sotfware: 1) ti-processor-sdk-linux-j721s2-evm-08_06_00_10-Linux-x86-Install.bin 

                 2) ti-processor-sdk-rtos-j721s2-evm-08_06_00_11.tar.gz 

  • 0
    TI__Guru** 113810 points

    Hi,

    The SDK for J721S2 is supporting the superset device. Therefore it can be used for both TDA4VL and TDA4AL.

    Let me know if you have any further questions. 

    Regards
    Karthik

  • 0 in reply to Karthik Ramanan
    Prodigy 140 points

    Yes, the SDK for J721S2 supports the superset device,

    and I used the EVM J721S2X SOMG01 EVM (TDA4VL / TDA4AL / TDA4VE).

    If the EVM includes all three SoC devices, how can I configure it to select TDA4VL specifically?

    Each SoC device has different features, as below.

  • 0 in reply to Haeyeon Song
    TI__Guru* 81806 points

    Hi,

    Please find the information in the below FAQ.

    (22) [FAQ] TDA4VM/TDA4VL/TDA4AL/TDA4VH/DRA821: How can we make the Jacinto SDK compatible for device variants? - Processors forum - Processors - TI E2E support forums

    You could refer the above for changes to be done to the SDK (such as clocking, DDR etc.) to be compatible to your device.

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 140 points

    Hello Nikhil,

    Thank you for the insightful information you have provided. It has been immensely helpful in enhancing our understanding of how to modify the SDK for different device variants.

    In addition to the information you've shared, we are also considering adjusting the clock speed of the ARM Core A72 from its current 2GHz to 1.2GHz for the TDA4VL device. Could you possibly guide us on the best way to approach this?

    Thank you in advance for your continued support.

    Best regards,
    Haeyeon

  • 0 in reply to Haeyeon Song
    TI__Guru* 81806 points

    Hi Haeyeon,

    In order to change the clock frequency of A72, please follow the below changes.

    PDK:

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    diff --git a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c
    index 2122081..df21405 100644
    --- a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c
    +++ b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c
    @@ -5168,7 +5168,7 @@ static const struct clk_data_div_reg clk_data_hsdiv0_16fft_main_7_hsdiv0 = {
    static const struct clk_data_div_reg clk_data_hsdiv0_16fft_main_8_hsdiv0 = {
    .data_div = {
    .n = 128,
    - .default_div = 1,
    + .default_div = 2,
    },
    .reg = 0x00680000UL + (0x1000UL * 8UL) + 0x80UL + (0x4UL * 0UL),
    .bit = 0,
    @@ -6417,8 +6417,8 @@ static const struct clk_data_pll_16fft clk_data_pllfracf2_ssmod_16fft_main_8 = {
    .vco_in_range_idx = J721S2_FREQ_RANGE_VCO_IN_PLLFRACF2_SSMOD_16FFT_MAIN_0,
    .fractional_support = STRUE,
    .devgrp = DEVGRP_01,
    - .pll_entries = pllfracf2_ssmod_16fft_main_14_entries,
    - .default_freq_idx = FREQ_PLLFRACF2_SSMOD_16FFT_MAIN_14_DEFAULT,
    + .pll_entries = pllfracf2_ssmod_16fft_main_5_entries,
    + .default_freq_idx = FREQ_PLLFRACF2_SSMOD_16FFT_MAIN_5_DEFAULT,
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Upon this changes, build the pdk libs and rebuild the DM.

    u-boot:

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    diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
    index 086f6da06c..bd49f1316a 100644
    --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
    +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
    @@ -35,7 +35,6 @@
    clocks = <&k3_clks 61 1>;
    assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
    assigned-clock-parents = <&k3_clks 61 2>;
    - assigned-clock-rates = <200000000>, <2000000000>;
    ti,sci = <&sms>;
    ti,sci-proc-id = <32>;
    ti,sci-host-id = <10>;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    After both the changes, do a clean rebuild of the u_boot and copy the files as shown below

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    cd ${PSDKLA}
    make u-boot_clean
    make u-boot
    sudo cp board-support/k3-image-gen-2022.01/tiboot3.bin /media/nikhil/BOOT/tiboot3.bin
    sudo cp board-support/u-boot_build/a72/tispl.bin /media/nikhil/BOOT/tispl.bin
    sudo cp board-support/u-boot_build/a72/u-boot.img /media/nikhil/BOOT/u-boot.img
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Verification Command:

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    k3conf dump clock 202
    k3conf dump clock 203
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Output:

    The A72 cores clock value is 1.2GHz.

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    root@j721s2-evm:~# k3conf dump clock 202
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-88-g982f5c2 built Wed Mar 1 18:42:41 UTC 2023) |
    | SoC | J721S2 SR1.0 |
    | SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.3--v08.06.03 (Chill Capybar)') |
    |--------------------------------------------------------------------------------|
    |-----------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |-----------------------------------------------------------------------------------------|
    | 202 | 0 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 1200000000 |
    |-----------------------------------------------------------------------------------------|
    root@j721s2-evm:~# k3conf dump clock 203
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-88-g982f5c2 built Wed Mar 1 18:42:41 UTC 2023) |
    | SoC | J721S2 SR1.0 |
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards,
    Nikhil