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TMDX654GPEVM: AM65x_GP_EVM Enabling ECC within U-boot

Benjamin Roytburd
Prodigy 30 points

Part Number: TMDX654GPEVM

Hello,


I am having issues enabling ECC within U-boot on my AM65x_GP_EVM. I used the AM65x_DRA80xM_EMIF_Tool_2.03 to generate my k3-am654-base-board-ddr4-1600MTs.dtsi file (which I then rebuild U-boot with). I followed the instructions within spracm1.pdf to enable ECC with this tool, and the following registers were updated 

#define DDRSS_V2H_CTL_REG 0x800073FF
#define DDRCTL_ECCCFG0 0x00000014
#define DDRPHY_DX4GCR0 0x40700204
#define DDRPHY_DX4GCR1 0x00007F7F
#define DDRPHY_DX4GCR2 0x00000000
#define DDRPHY_DX4GCR3 0xFFC0010B

(note this issue is very similar to https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1002828/tmdx654idkevm-enabling-ddr4-ecc, if not the same).

But, when I load U-boot onto the AM65x_GP_EVM, I get the following error:

U-Boot SPL 2021.01-gdc85eeb6 (Apr 21 2023 - 23:05:34 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
write_leveling_adjustment: ERROR: Write Leveling adjustment failed
DRAM init failed: -22

resetting ...

Not sure if there is an issue with the tool or a configuration I am missing. How can I enable ECC with U-boot on this board? 




  • 0
    Prodigy 30 points

    Did some testing, found something very interesting, when keeping ECC off and the DX4GCRn registers their defaults of

    #define DDRPHY_DX4GCR0 0x40703220
    #define DDRPHY_DX4GCR1 0x55556000
    #define DDRPHY_DX4GCR2 0xAAAA0000
    #define DDRPHY_DX4GCR3 0xFFE18587

    And setting DX0-3 GCRn registers to all be 

    #define DDRPHY_DXnGCR0 0x40700204
    #define DDRPHY_DXnGCR1 0x00007FFF
    #define DDRPHY_DXnGCR2 0x00000000
    #define DDRPHY_DXnGCR3 0xFFC0010B

    I get no write leveling adjustment failures, it is only when I set those DX4GCRn to the changes generated by AM65x_DRA80xM_EMIF_Tool_2.03 do I get those write leveling errors. This is all with ECC off... so there is in issue with how DX4GCRn is being configured. Not sure what that issue is though.




  • 0 in reply to Benjamin Roytburd
    Prodigy 30 points

    Keeping this thread going in case others are curious, using the AM65x_DRA80xM_EMIF_Tool_2.03 tools generated GEL file I was able to initialize DDR ECC. One thing I notice is that there are differences in how U-boot initializes DDR versus how the DDR GEL script does it. 

    For instance registers such as DDRSS_DDRPHY_DX4GTR0, DDRSS_DDRPHY_DX4GCR5, and DDRSS_DDRPHY_DX4GCR4 are not set within the file k3-am654-ddrss.c. 

    Why do the GEL file and the actual U-boot code behave differently? Adding the changes from the GEL file seem to stop that write leveling error, but U-boot still hangs. 

  • 0 in reply to Benjamin Roytburd
    TI__Expert 8480 points

    Hello Benjamin,


    I can see the same issue you are seeing. I have two AM65x IDK boards. One is Silicon SR2.0 and the other seems to be Silicon SR1.0. The board that is Silicon SR1.0 is the one shows the write leveling adjustment error and the DRAM init fail. Which silicon revision is your board?

    Silicon SR2.0 does not have this particular issue, I will compare DDR ICs and update the EMIF tool to see if this fixes the issue. 

    regards,

    Judith

  • 0 in reply to Judith Mendez
    Prodigy 30 points

    Judith, I got good news! I solved it. I am using SR1.0, and I believe the issue to have to do with the U-boot code itself. I will submit a PR to U-boot in the future, but in short, what you should do is:

    1. Use the generated GEL scripts from AM65x_DRA80xM_EMIF_Tool_2.03 and see if you can initialize DDR and dump the ECC regs from there, if that works you know that DDR ECC should work on your chip

    2. Look at the U-boot file U-boot/drivers/ram/k3-am654-ddrss.c and compare the PHY, CTL, and training register writes to the file M4_DDR_Config.gel, you will probably see some missing register writes related to DX2, DX3, and DX4, make sure you add these missing register writes. 

    3. Also follow https://www.ti.com/lit/an/spracm1/spracm1.pdf to properly prime ECC, take care to make sure you are actually priming the amount of bytes you mean to, (i.e. 2 GB of data would be 0x80000000) 

    With all of this, that write leveling error disappears and I am able to boot into U-boot as well as my application

  • 0 in reply to Benjamin Roytburd
    TI__Expert 8480 points

    Glad to see you found the issue. Nice work. Have a great day!