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In TMDSSK3358, all DQ bits in each of byte lanes are swapped for DDR3.
I understand the following about swapping DDR3 data lanes, is that correct?
- In AM335x, for DDR3 and DDR3L, byte lanes and all DQ bits in each of byte lanes can be swapped because Write leveling is not supported and therefore prime DQ bits are not used.
That is described in the post at the link below.
e2e.ti.com/.../am4376-about-ddr3-data-line-swapping
"AM335x: similar to AM437x, DQ swizzle is allowed within a byte lane for DDR3/3L designs (cannot swizzle DQS or DM). Byte lanes can also be swapped (must swap DQx, DM and DQSx as a group). It is true that AM335x does not support hardware leveling, the leveling is performed using a software algorithm."
Why is the swapping data lanes needed? Is it needed for more appropriate routing?
Best regards,
Daisuke
