• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 99 subscribers
  • Views 326 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: TDA4VM: CPTS Reference Clock Frequency Adjust & ppstest time stamp result not equal to 1s

Kevin Peng
Expert 3772 points
Part Number: TDA4VM

Hi TI Experts,

Customer is trying to adjust the CPTS reference clock frequency: DEV_NASS0_CPTS_0_RCLK. They want it to be at 1Ghz.

However, they have added the corresponding configuration of CPTS in both board_pll.c & board_clock.c in SBL shown below, but it does not work.

Could you help on this to see if any other places need to be changed to adjust DEV_NASS0_CPTS_0_RCLK frequency?

Another question is that customer finds ppstest time stamp result mismatches with the clock frequency.

Firstly, they have created /dev/pps0 successfully from the below link.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1223023/tda4vm-cannot-enable-pps-find-it-in-dev

They are using HWITSPUSHIN as input & NAVSS0 HW8_TS_PUS as output

However, from the ppstest result, the time interval is around 0.8s not equal to expected 1s.

Could you provide some feedback & suggestions about it?

Kind Regards,

Kevin

  • 0
    TI__Guru* 77754 points

    Kevin

    Please refer the below PLL defaults (ffor crystal 19.2MHz) for TDA4VM from tisci doc.

    1. Can you check the register for the clock selection i.e. CTTLMMR_NAVSS_CLKSEL (0x0010_8098).

    2. To get 1000MHz for this clock, either one of the HSDIVs need to change and that will have an effect on other clocks as well. Orr we need to find which default input to the RCLK clk mux gives 1GHz.

    3. What error do you see with the SBL modification? Can you increase log level and check?

    Regards

    Karan