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TMDS64EVM: PTP - Generate PPS and custom frequency sync signal with CPSW and PRU-ICSSG

Part Number: TMDS64EVM


Dear TI support team,

Our goal is to get a PPS signal and two other, custom frequency periodic signals (let's say 2kHz and 2.4kHz) synchronized with PTP from the AM64x SoC physical pins. At the end, we hope to achieve this over redundant ethernet networks (i.e. PRP and HSR), and using as much PRU-ICSSG offload as possible.

I've been testing PTP and PPS features on TMDS64EVM using the latest Processor SDK (08_06_00_42 at the moment) with both tisdk-base-image and tisdk-default-image builds based on 1.2. Building the SDK.
So far, I've had quite a few issues with certain functions that the SoC is said to be capable of. Here are my findings on which some clarification would be highly appreciated:

1.) CPSW ethernet port (eth0) works with PTP and PPS as expected. Although I had to do some digging around to find that the following modifications are required to be able to see the PPS signal on a physical pin:

	/* Example of the timesync routing */
	mcu_cpts_pps: mcu-cpts-pps {
		pinctrl-single,pins = <
			/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
			TS_OFFSET(37, 22)
			/* pps [cpts genf1] in22 -> out24 [SYNC0_OUT pin] */
			TS_OFFSET(24, 22)
		>;
	};

Not sure though, if I want it to be routed to another external pin, or use a different genf output of the module (e.g for a different frequency) where do I find the numbers to refer to those signals (like 22 and 24 here).

2.) testptp -d /dev/ptp0 -P 1
enables the PPS from the CPTS. OK, I can see it now on the scope. My understanding is (looking at the testptp help menu, because it doesn't seem to be documented in any TI resource) that e.g
testptp -d /dev/ptp0 -p 1000000 -w 500000 -H 0
command should produce from that same clock a 1kHz frequency, 50% duty cycle and 0ns offset periodic signal. Is that correct? Because nothing happens when issuing the command. I also tried manually writing the registers from user-space that are claimed to control the genf_n signal generators (following the TRM), but writing any value to them is also ineffective. How is it possible to generate a custom frequency sync signal from CPTS?

3.) Using an ethernet port driven by PRU-ICSSG (either one of eth1 or eth2 if ...icssg-dualemac... .dtbo is applied) and hw clock attached to it, PTP works as expected. After finding the following section in DTS:

	icssg1_iep0_pins_default: icssg1-iep0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
		>;
	};

and after enabling PPS with testptp, I can again see the PPS signal on the corresponding header of the am64xxevm. Although after adding
AM64X_IOPAD(0x00FC, PIN_OUTPUT, 2) /* (U7) PRG1_PRU0_GPO17.PRG1_IEP0_EDC_SYNC_OUT1 */
I don't know how to route a PPS signal to SYNC_OUT1 as well.

Also, PPS is not in phase with the master's PPS and always has a random offset between 0-1 sec. How can this be solved? (Just to clarify, when running ptp4l there is no drift, but when disabling and reenabling the PPS, the offset changes)

4.) testptp -d /dev/ptp0 -p 1000000 -w 500000 -H 0
This command does have an effect here, but not what I tell it to do. -w and -H options change nothing, and -p period length can be changed to a maximum frequency of 200Hz too. For -p smaller than 5000000ns the period is always 5ms no matter what. Is this tool supposed to work properly? I also looked at the registers here that are supposed to control the period, on time and phase of the periodic signal, found all of them to contain 0x00000000 (IEP_SYNC_START_REG, IEP_SYNC0_PERIOD_REG, IEP_SYNC_PWIDTH_REG). Writing to them has no effect. Can these parameters be set from user-space?

5.) Finally, PRP/HSR. There is no mention of PRP/HSR using the PRU subsystem in the AM64x PSDK so I followed the one for AM65x. They contain the same PRU-ICSSG and some of the firmware files in /lib/firmware in Am64x rootfs have *am65* in their name anyways...

ip link add name hsr0 type hsr slave1 eth1 slave2 eth2 supervision 45 version 1

command does not work in tisdk-base-image but does in tisdk-default-image. I read somewhere that you are aware of the issue and working on fixing it. Okay. So using tisdk-default-image, the prp0 or hsr0 interface can be succesfully brought up, but the
ethtool -K eth1 prp-rx-offload on

command still doesn't work, which I suppose should load the prp firmware into the PRU? Does this mean that in the prp0 interface the PRU-ICSSG only passes the packets through without processing and the handling of the protocol still happens in Linux? Either way, ptp4l works properly with a link in either eth1 or eth2 ports, and using /dev/ptp2 which should point to a hw clock implemented in IEP inside PRUSS.

PPS and custom frequency periodic signal don't work with /dev/ptp2 though when prp0 interface is brought up. Should they in redundant modes?

Thank you for your assistance in advance,

Gábor

  • There are several questions on this post responding to some of them. In general I recommend asking only one or a couple questions per post. For example one post on HSR support and issues, another on PRP and issues, and a third on PPS.

    Regarding PRP:

    PRP https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/HSR_PRP.html?highlight=prp using kernel and any two Ethernet interfaces should be fine today. The duplicate discard with some benefit to CPU loaf would be the main point of offloading to ICSSG. Duplicate drop is not enabled in 8.6 release. Enabling it is aligned with HSR release which is in 9.2.

    5.) Finally, PRP/HSR. There is no mention of PRP/HSR using the PRU subsystem in the AM64x PSDK so I followed the one for AM65x. They contain the same PRU-ICSSG and some of the firmware files in /lib/firmware in Am64x rootfs have *am65* in their name anyways...

    We are updating the Linux HSR on ICSSG support to 1G in AM64x. The existing steps are using the Linux kernel HSR (basically switching in the Ethernet device driver), and then the 100M ICSS based offload (what the AM65x documentation refers to), that on AM64x is only validated on MCU+ and R5. The schedule for 1G HSR in Linux on AM64x is:

    Processor SDK 9.0

    Processor SDK 9.1

    Processor SDK 9.2

    HSR 1 G Switch offload

    HSR 1G offload: TX tag insertion and packet duplication

    HSR 1G offload: RX tag removal and packet duplicate discard 

    How is it possible to generate a custom frequency sync signal from CPTS?

    Yes genf is for this purpose and what you are trying out seems to be the right thing.

    Also, PPS is not in phase with the master's PPS and always has a random offset between 0-1 sec. How can this be solved? (Just to clarify, when running ptp4l there is no drift, but when disabling and reenabling the PPS, the offset changes)

    Your observations match what we have seen, there is some offset setup issue with testptp on AM64x.

      Pekka

  • Hi Pekka,

    Thank you for your answer. Regarding my other questions about PPS, can I expect to have them answered in this thread, or would you recommend opening a separate one?

    Also, is there a publicly available SDK release plan that is up-to-date? https://www.ti.com/lit/zip/sprcaj4 this one doesn't appear to have been updated since 1Q22.

    Regards,

    Gábor

  • Also, is there a publicly available SDK release plan that is up-to-date? https://www.ti.com/lit/zip/sprcaj4 this one doesn't appear to have been updated since 1Q22.

    No unfortunately we stopped using the build sheet with the future AM64x SDK releases. The roadmap of SW SDK is not currently being shared publicly.

    Also, PPS is not in phase with the master's PPS and always has a random offset between 0-1 sec. How can this be solved? (Just to clarify, when running ptp4l there is no drift, but when disabling and reenabling the PPS, the offset changes)
    Regarding my other questions about PPS, can I expect to have them answered in this thread, or would you recommend opening a separate one?

    I think this offset issue with testptp is random with HSR is what is still left open? Specific post or this is fine. Can you shared the LAN topology and what commands have you run on which boards. Running CPSW3G based and without HSR, run the same commands, is the behavior the same?

      Pekka

  • The questions I feel have not been addressed are the ones written in bold letters from 1.) and 4.).

    Regarding question 2.), I understand that there are 6 genf signals for this purpose, and they can be routed to SYNCn_OUT pins (n =0,1,2,3) but is there software support to set the actual parameters of each genf signal? Because testptp does not have any effect other than enabling 1PPS.

    Also, if you are aware as well of the incorrect behaviour of testptp 1PPS and larger frequency sync signals with PRU, can you at least tell me if there is a plan to fix them in future SDK releases, or testptp will only be usable for basic experiments.

    Thank you,

    Gábor

  • Hello Gábor,

    For more information about time sync router inputs and outputs you can reference this FAQ:
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1061474/faq-am64x-what-is-the-time-sync-router-for-how-do-i-use-it

    I believe by now the TRM has been updated to include this information summarized in the time sync chapter, but it's late my time and I'm running out of time to check tonight.

    I will have to let Pekka comment on the testptp question.

    Regards,

    Nick

  • Pekka,

    Can we expect an update on the mentioned issues? It is very important for us to know now if the PPS and other frequency sync signals will work correctly in the future, especially with the PRU. If the answer is no, or not sure, we will have to make modifications to our PCB design to generate them using other hardware.

    Running CPSW3G based and without HSR, run the same commands, is the behavior the same?

    As I mentioned in the original post in point 2.), CPSW could only produce a 1PPS signal and nothing else.

    Can you shared the LAN topology and what commands have you run on which boards

    We are only using one EVM as a slave, with a timeserver as a master, and one UTP cable between them connected to either of the PRU ports in PRP mode or in normal (non-redundant) mode.

    testptp -d /dev/ptp0 -p 1000000 -w 500000 -H 0
    command produces a signal only from the ptp device associated with a PRU-driven port and only in non-redundant mode. This is when the mentioned problem occurs: the sync signal is not in phase and the offset seems to be random every time.

  • In the latest (f revision) TRM there is a little more on time sync router:

    There is up to 12 pins to generate PPS and other frequencies. 4 SYNCn_OUT pins (n =0,1,2,3) from the output of the time sync router pictured above. And then a further 4 from each ICSS (2 EDC_SYNCOUT pins per IEP, IEP is the counter with the compare similar to the genf from CPTS in CPSW). The ICSSG IEP SYNC (same as EDC_SYNCOUT) can be connected to the time sync router and then to the SYNCn_OUT pins (n =0,1,2,3). So that HW path should give you the most flexibility with using the SYNCn_OUT pins. The input id numbers are also now in the TRM see Table 9-92. TIMESYNC_INTRTR0 Interrupt Map.

    The ptp stack is disciplining the CPTS (with CPSW3G) or IEP (ICSSG) hardware underneath, which in the HSR offloaded to ICSSG-PRU will be using the IEP as the /dev/ptp device.

    With the HSR switching offload firmware in 9.0 SDK, testptp will work using the IEP based SYNC_OUT.

  • I think this was closed with correct PPS showing up with 1.8V GPIO. The device tree setting will be in the SDK documentation update for ICSSG based PPS:

    To enable PPS on AM64x, the hardware pin PRG0_IEP0EDC_SYNC_OUT0 needs to be enabled.

    icssg0_iep0_pins_default: icssg0-iep0-pins-default {
        pinctrl-single,pins = <
            AM64X_IOPAD(0x01AC, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
    >;