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Original question:

PROCESSOR-SDK-J721E: How to detect good TLP arriving at PCIe.

PROCESSOR-SDK-J721E: PCIe: How does an application know that inbound data has been received from the link?

Simon Gibbs
Prodigy 80 points
Part Number: PROCESSOR-SDK-J721E

In the example code that I have, an application polls a buffer until it contains a value which it expects to receive from the Endpoint side. 

The application is running as a FreeRTOS task. How can it receive an interrupt/message that the data has arrived?

  • 0
    TI__Mastermind 23125 points

    Simon, 

    I can think of two methods, depending on your preferences:

    1. EP may send an MSI-X interrupt at end of its transfer to the RC. If EP uses DMA to transfer, then the DMA completion may trigger a MSI-X to RC;

    2. EP writes to a CTRLMMR_IPC_SETn register at the end of its transfer. These registers will trigger a interrupt to the GIC. This will require to map RC's CTRLMMR space to the EP. 

    Let us know if either can work for you. 

    Jian

  • 0
    Prodigy 80 points

    Hi Jian,

    I don't think either method allows us to interrupt the MCU1_0. We have a requirement to only write software for the MCU1_0. Is this possible?

    Simon

  • 0 in reply to Simon Gibbs
    TI__Guru 50403 points

    Hi Simon,

    For the first MSI-X interrupt option we mentioned in previous post, we are currently looking into whether it is possible to route to MCU1_0. Currently, it is uncertain, so the recommendation are these other options which we are fairly confident that it would work with MCU1_0:

    1. The MAIN2MCU_PLS_INTRTR0 should be able to route PCIE0 and PCIE1 to the MCU1_0: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/interrupt_cfg.html#main2mcu-pls-intrtr0-interrupt-router-input-sources. If your EP device supports legacy interrupt mode, then it should be able to set up using this interrupt router to interrupt MCU1_0.
    2. Using CTRLMMR_IPC_SETn as mentioned before, except using the CTRLMMR_MCU_IP_SETn registers which are the MCU equivalent of these MAIN domain registers. Doing writes to these registers would trigger an interrupt on the core. However, as a warning, this requires unlocking the block of CTRLMMR registers that has the CTRLMMR_MCU_IP_SETn registers, so if there are some rogue applications that periodically tries to change other CTRLMMR registers it could cause problems. On the other hand, this option would be pretty straightforward since the EP basically just needs to be able to write to this register to trigger an interrupt.

    Regards,

    Takuma