Other Parts Discussed in Thread: SK-AM64B, SYSCONFIG, DP83869
Hi,
we are trying to setup the Enet Layer 2 CPSW SWITCH Example with the SK-AM64B Evaluation Board.
Empty project can be started and debugged. Enet-Example works also very well.
CPSW SWITCH Example can be started but is stuck after Port 1 link up.
Got the the example from MCU SDK C:\ti\mcu_plus_sdk_am64x_08_05_00_24.
Output from UART Terminal:
========================== Layer 2 CPSW SWITCH Test ========================== Init all peripheral clocks ---------------------------------------------- Enabling clocks! Create RX tasks ---------------------------------------------- cpsw-3g: Create RX task Open all peripherals ---------------------------------------------- cpsw-3g: Open enet EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 3 To 2 Init all configs ---------------------------------------------- cpsw-3g: init config Mdio_open: MDIO Manual_Mode enabled cpsw-3g: Open port 1 EnetPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK cpsw-3g: Open port 2 PHY 0 is alive PHY 1 is alive Attach core id 1 on all peripherals ---------------------------------------------- cpsw-3g: Attach core cpsw-3g: Open DMA initQs() txFreePktInfoQ initialized with 16 pkts cpsw-3g: Waiting for link up... Cpsw_handleLinkUp: Port 1: Link up: 1-Gbps Full-Duplex MAC Port 1: link up cpsw-3g: Port 1 link is up
Sysconfig File is out of the example. It seems like second PHY interface is not configured.
