TMS320C6655: ECC remove and power consumption summary

Daniel,

Please let us know the source of the picture you have posted.

https://www.ti.com/lit/an/spraco4a/spraco4a.pdf

Please refer this doc for EDC and ECC details.

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In general, actually in the control registers of EDC/ECC, there will always be an option to enable or disable the ECC...

----> One of the examples here----> for MSMC SRAM refer this doc at page no: 39, https://www.ti.com/lit/ug/spruhj6/spruhj6.pdf

        The 30th bit of register "SMEDCC" is the ECM field to disable or enable the ECC

Error Correction Mode

0 = Disables error correction

1 = Enables error correction

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Similarly, for other interfaces ( EMIF) / memories like SDRAM, please refer to the appropriate sections in the datasheet.

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DDR3 memory controller -- https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf

2.17 ECC For data integrity, the DDR3 memory controller supports ECC on the data written to or read from the ECC protected address ranges in memory. The ECC algorithm is a single-error-correct-double-error-detect (SECDED) algorithm and uses the (72,64) Hamming code. Eight-bit ECC is calculated over 64-bit data quanta. ECC is enabled by setting ECC_EN = 1 in the ECC Control register. ECC is disabled by setting ECC_EN=0. By default, ECC_EN=0. The address ranges can be programmed in the ECC Address Range 1 and 2 register. The system must ensure that any bursts accesses starting in the ECC protected region must not cross over into the unprotected region and vice-versa. NOTE: The ECC is stored inside the SDRAM during writes. After enabling ECC and before performing any functional reads or writes, all DDR3 memory space configured as ECC should be first written with known data that is 64-bit aligned and multiples of 64-bit. This is to ensure the correct ECC values are stored in the ECC SDRAM prior to functional use.

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The question on power consumption summary will be answered by Kyle.

Regards

Shankari G

Daniel,

Refer to this thread for power consumption links:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/780921/tms320c6654-typical-power-consumption-of-c6654-c6672-and-c6674

Regards,

Kyle

Daniel,

The link I sent has a post by Tom Johnson that is highlighted green including these links (middle one is C6655 xls) :

Power Consumption Summary for KeyStone C66x Devices Application Report (SPRABI5B) at www.ti.com/.../sprabi5

C6655 Power Consumption Model (SPRM601) at www.ti.com/.../sprm601

TMS320C6657/55/54/52 Power-efficient DSPs for applications requiring high performance (SPRT629) at www.ti.com/.../sprt629

Regards,

Kyle