TDA4VM: TSN (Time-Sensitive Networking) features for TDA4VM and TDA4VH

hello any feedback on this? 

Hi Jon,

Sorry for the delayed response.

Jon Bilbao said:

Is there any documentation available for using and configuring TSN on QNX, Linux and FreeRTOS?

TSN features were supported in Linux SDK. You can refer to Linux SDK Documentation for TSN features.
FreeRTOS has only PPS support, but that is also for testing purpose and not for production support.

Jon Bilbao said:

Are there any examples for TSN within the SDK for TDA4VM?

Refer to SDK Documentation mentioned above for the examples and testing the TSN features.

Jon Bilbao said:

Does TSN features supported on CPSW9G in TDA4VH is same for the TDA4VM?

Yes, TSN features were common across CPSW in TDA4VH and TDA4VM.


Also, Please refer to FAQ [How to enable Native Linux driver for CPSW9G]. As TSN features were supported only in Native Linux Driver mode for CPSW9G.


Best Regards,
Sudheer

Hi Sudheer,

Thank you for the answer.

This documentation is specifically for Linux. Do you have any documents and examples regarding the usage and configuration for QNX?

Could you please provide us with a roadmap for TSN features on TDA4VM? (Alternatively, do you have a list of TSN services that are currently supported on QNX)?

Best Regards,

Marko.

Hi,

Marko Milosevic said:

This documentation is specifically for Linux

Yes, In Linux we have support for CPSW9G Native Linux driver instead of Ethfw based use-case.
CBS, EST configuration using "tc" commands in Linux and IET via ethtool private IOCTL.
PTP we have ptp4l application in Linux.

As informed above In RTOS we have only PTP support that to stack is only for testing purpose and not for production support.

Marko Milosevic said:

Could you please provide us with a roadmap for TSN features on TDA4VM? (Alternatively, do you have a list of TSN services that are currently supported on QNX)?

In QNX also we have PTP support but not other features, please refer to QNX SDK documentation.

We have plan to support TSN features in RTOS SDK in coming SDK releases.

Best Regards,
Sudheer

Hi,

Doredla Sudheer Kumar said:

In QNX also we have PTP support but not other features,

Do you have plan to support TSN features (CBS, EST...) in coming QNX SDK releases?

Best Regards,

Marko.

Hi,

Marko Milosevic said:

Do you have plan to support TSN features (CBS, EST...) in coming QNX SDK releases?

These TSN features are not planned and are not available for io-pkt driver & network stack from QNX, and also io-pkt driver is going to phased out.
If required you can directly contact QNX and request this on the new io-sock driver & network stack.

Best Regards,
Sudheer

Hi,

We have one more question regarding the CPSW9G switch on TDA4VM and TDA4VH. QNX is running on the A72 core, and Autosar is running on the R5F cores.

Is it possible for the MCU1_0 core (MCU domain) to access the CPSW9G switch and send Ethernet frames? If so, who will provide the Ethernet MCAL module for CPSW9G, Vector or TI?

Best Regards,

Marko.

Hi Sudher,

1.  What does "TI RTOS Switch" mean in the image below? Is it a separate processor that configures the CPSW9G switch?

2. Can Autosar (on MAIN or on MCU domain) configure the CPSW9G switch? Or it is only possible with the RTOS?

3. Is it possible to have a configured CPSW9G switch without having an RTOS in the system?

4. Is there more elegant solution for this FAQ?

5. Who configures the CPSW2G switch in the MCU domain? Can AUTOSAR on MCU1_0 handle that?

6. Who is responsible for configuring the CPSW2G switch in the MAIN domain on TDA4VH?  Can it be configured by Linux, QNX (A72), or Autosar on the R5F main domain?

Best Regards,

Marko.

Hi,

One additional question:

1a) What is the IPC control path in the image from the previous question?

Regards,

Marko

Hi Sudheer,

Thank you for the quick response. We have questions regarding bandwidth and CPU load.

1. Do you know what the bandwidth is for CPPI Port 0 on CPSW9G?

2. From this link  "CPU utilization was captured as the total percentage used across all cores on the device"  Is this a mistake? If not, Can you provide us with more detailed explanation of how the utilization is measured (This means that all cores are being utilized with the value obtained from the column in the table)?

Best Regards,
Marko.

Hi,

Marko Milosevic said:

1. Do you know what the bandwidth is for CPPI Port 0 on CPSW9G?

It can handle the whole data coming from all 8 external ports.

Marko Milosevic said:

From this link  "CPU utilization was captured as the total percentage used across all cores on the device"  Is this a mistake? If not, Can you provide us with more detailed explanation of how the utilization is measured (This means that all cores are being utilized with the value obtained from the column in the table)?

May be it means from the cores running in Linux point of view. In case of J721E: two cores of A72 were available, but interrupt being handing by single core till 8.5 SDK versions, from SDK 8.6 interrupt shares by cores i.e. IRQ balancing support added to kernel.

Best Regards,
Sudheer

Hi Sudher,

Hi,

Marko Milosevic said:

When CPSW9G is in switch mode, do we need to perform the steps for bridge setup [LINK]?

It is recommended to run bridge setup when the CPSW9G is in switch mode to avail switch functionality. Default in Native Linux driver CPSW9G is not in switch mode it will be like 8 individual MAC only Ports.
Until setting/enabling the switch mode [LINK] CPSW9G is in MAC only mode with multiple ports.

Marko Milosevic said:

Can the switch function without this bridge setup?

No, you have to create Bridge for switch functionality.

Marko Milosevic said:

1a) For PTP setup [LINK], is the bridge setup mandatory, or does it work without it?

No, PTP will work even without Bridge. But, you have to run PTP slave only (one HW clock to sync) on one port not on multiple ports, whereas PTP master can run on multiple ports.

Marko Milosevic said:

Is it possible to set the CPSW_ALE_CONTROL field ALE_ENABLE runtime (serial) using a command?

No, Also it is not recommended to enable and disable ALE ant runtime.

Marko Milosevic said:

Is there a tool or application available for switch configuration?

yes, you can setting/enabling the switch mode [LINK].

Marko Milosevic said:

1. How can we add a static multicast entry in ALE when the switch is in switch mode?

             3a) Can we modify the file am65-cpsw-nuss.c (located at board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/net/ethernet/ti/am65-cpsw-nuss.c) to add multicast using the function cpsw_ale_add_mcast, or is there another recommended way to do it?

You can add using FDBs and MDBs [LINK], and we are not recommended to modify the driver for the same.

Marko Milosevic said:

What is the difference between the outputs of these commands:

a) switch-config -d

b) switch-config --ndev eth0 -d

I obtained different ALE tables with a) and b)

It should not be if default network interface is eth0.
It is recommended always to pass network interface for which you need ALE entries table.
eth0 is for CPSW2G and eth1 to eth8 for CPSW9G.

Marko Milosevic said:

We would like to add a static multicast entry in ALE for the CPSW9G switch and disable dynamic learning. What is the easiest way to accomplish this?

For MAC address you can use FDB and MDBs for disabling of dynamic learning we have to modify driver there is no option for dynamic/runtime control.
Set "ALE_PORT_NOLEARN" from "am65_cpsw_init_port_switch_ale" function similar to configuring in "am65_cpsw_init_port_emac_ale" function in drivers/net/ethernet/ti/am65-cpsw-nuss.c file and rebuild the kernel.

Marko Milosevic said:

 6) Example entry in ALE:

          12 : type: mcast, addr = 33:33:00:00:00:fb, mcast_state = f, no super, port_mask = 0x1

          What does "port_mask" mean (0x1 means port 1?) ?

Port Mask is bit filed info corresponding to Port numbers including the Host port.
0x1 means only Host Port, 0x2 means only external Port-1, 0x3 means both Host Port and External Port-1.
Based on the Port Mask, Multicast frames will be forwarded to ports which has Mask bit set.

Best Regards,
Sudheer

Hi Sudheer,

Thank you for the detailed answers.

Doredla Sudheer Kumar said:

For MAC address you can use FDB and MDBs

I executed the following command

bridge mdb add dev br0 port eth3 grp 239.1.1.1 permanent

and with this command switch-config --ndev eth3 -d I got port_mask 0

 type: mcast, vid = 1, addr = 01:00:5e:01:01:01, mcast_state = f, no super, port_mask = 0x0

I would like to add the multicast address 239.1.1.1 in ALE. How do I set the port mask?

I need to set the port mask for both the host port and port 3. The multicast address 239.1.1.1, which enters on port 1 (eth3), should be forwarded to the Host port, and also forwarded to port 3 (eth1).

Also I have one question about PTP and EST on CPSW9G

We are looking to configure PTP and EST on the two TDA4VH boards. In this setup, one TDA4VH board will act as the Master, and the second board will be the Slave [LINK]. Both TDA4VH boards will have EST configured [LINK]. The cycle time is set to 1ms, with Board 1 sending messages in the first 500 microseconds, and Board 2 sending messages in the second 500 microseconds.  Now, the question is: How can we verify that this setup is working correctly?  Is there any function that allows us to obtain the synchronized time ?
For example, when using the iperf3 tool for sending messages, we would like to see, using tools like tcpdump or Wireshark, that messages are received on both boards at regular intervals:
Board VH2 receives messages between 0 and 499 microseconds.
Board VH1 receives messages between 500 and 999 microseconds.
We wonder if there is a way to print the synchronized time in the terminal when a message is received, or if we need to manually calculate and add the Master's offset to the VH2 system clock on the Slave side?

Best Regards,

Marko.

Hi Tanmay,

I executed the following commands on two boards but port_mask is 0x0 ( type: mcast, vid = 1, addr = 01:00:5e:01:01:01, mcast_state = f, no super, port_mask = 0x0).

devlink dev param set platform/c000000.ethernet name switch_mode value true cmode runtime
ip link add name br0 type bridge
ip link set dev br0 type bridge ageing_time 1000
ip link set dev eth1 up
ip link set dev eth2 up
ip link set dev eth3 up
ip link set dev eth4 up
ip link set dev eth1 master br0
ip link set dev eth2 master br0
ip link set dev eth3 master br0
ip link set dev eth4 master br0
ip link set dev br0 up
ip link set dev br0 type bridge vlan_filtering 1
bridge vlan add dev br0 vid 1 pvid untagged self
bridge link set dev eth1 mcast_flood off
bridge link set dev eth2 mcast_flood off
bridge link set dev eth3 mcast_flood off
bridge link set dev eth4 mcast_flood off

bridge mdb add dev br0 port eth1 grp 239.1.1.1 permanent

1. Are these commands correct?
2. Which command should I execute to set the port_mask to 0x3 (forwarding the frame to both the Host Port and Port 1) for the address 239.1.1.1?

Regards,

Marko.

Hi Marko,

The host port mask appears to a bug in the driver. I have created a ticket for this and will keep you updated on its progress.

Regards,
Tanmay