TDA4AL-Q1: version 0806: mcu2_0's GPIO interrupt setup failed，Sciclient_rmIrqSet call failed

Sorry, the print is wrong, here is the updated print

I run a loop on IRQ number from 0 to 512 on R5F core and Sciclient_rmIrqSet function all failed

I tried to use other banks and found that bank5 can use interrupt number 396, bank6 can use interrupt number 397, bank7 can use interrupt number 399,The interrupt numbers matches the interrupt routing table, but TDA4AL only writes GPIO0_0 to GPIO0_65, bank5 is converted to GPIO0_80, is it beyond the pin count of TDA4AL, right?

bank5 396
bank6 397
bank7 398

I configured 0x0060004C to turn on GPIO0_59 rising edge detection for 0xFF000000 and the loop read 0x0060005C, no interrupt flag is generated, but I give GPIO0_59 input a level of 8KHZ and I don't know why this is so, I also checked that the 0x00600038 value is 0xFF77FFFF, which means that the direction of the GPIO0_59 is input

/dev/mem opened.
Memory mapped at address 0xffffb8fe8000.
Read at address  0x00600038 (0xffffb8fe8038): 0xFF77FFFF
j721s2-evm:~# devmem2 0x0060004C
/dev/mem opened.
Memory mapped at address 0xffff9e8a5000.
Read at address  0x0060004C (0xffff9e8a504c): 0xFF000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffffa32bd000.
Read at address  0x0060005C (0xffffa32bd05c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffff91c97000.
Read at address  0x0060005C (0xffff91c9705c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffff891c8000.
Read at address  0x0060005C (0xffff891c805c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffff8c594000.
Read at address  0x0060005C (0xffff8c59405c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffff8cf3e000.
Read at address  0x0060005C (0xffff8cf3e05c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffffa5a47000.
Read at address  0x0060005C (0xffffa5a4705c): 0x00000000
j721s2-evm:~# devmem2 0x0060005C
/dev/mem opened.
Memory mapped at address 0xffff9c8ef000.
Read at address  0x0060005C (0xffff9c8ef05c): 0x00000000

Hi Renf Shi,

Interrupt number 396 onwards are IRQ numbers of R5F, to which GPIO Mux outputs are connected. This does not indicate the Bank number of the GPIO input. We should be able to connect valid GPIO Bank to one of this GPIO Mux output and should be able to use irq number 396 onwards. 

Are you planning to use Bank interrupt for processing? If then we can use existing code to configure and connect GPIO bank interrupt to R5F IRQ. But you require individual GPIO interrupt, this will require changes in the current driver.. 

For Bank interrupt, can you please try below parameters.

src_id = J721S2_DEV_GPIO0

src_index = bank number

dst_id = ID of the R5F, J721S2_DEV_R5FSS0_CORE0 for mcu2_0.

dst_index = irq number of R5F ie 396.

Regards,

Brijesh

Hello, I follow the parameters you gave, Sciclient_rmIrqSet function or return -1, the following modification of the GPIO_socConfigIntrPath function

int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,bool setIntrPath)
{

    GPIO_v0_HwAttrs   *cfg = (GPIO_v0_HwAttrs *)hwAttrs;
    GPIO_IntCfg       *intCfg;
    uint32_t           bankNum;
	int32_t retVal=CSL_PASS;

    intCfg = cfg->intCfg;

    struct tisci_msg_rm_irq_set_req     rmIrqReq     = {0};
    struct tisci_msg_rm_irq_release_req rmIrqRelease = {0};
    struct tisci_msg_rm_irq_set_resp    rmIrqResp    = {0};

    uint16_t ir_id = 0U, src_id = 0U, src_index = 0U, dst_id, dst_host_irq, irq_range_start, irq_range_num;

    /* Input parameter validation */
    bankNum = pinNum/16U; /* Each GPIO bank has 16 pins */

    /* GPIO uses bank interrupts. So choose the bank interrupts from bus_gpio_bank with valid values from
     * the DMSC firmware user guide */
    /* We route bank interrupts to the cpu interrupts */
    switch (cfg->baseAddr)
    {
        case (uint32_t)CSL_WKUP_GPIO0_BASE:
            ir_id = TISCI_DEV_WKUP_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_WKUP_GPIO0;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721S2_DEV_WKUP_GPIO0 */
            break;
        case (uint32_t)CSL_WKUP_GPIO1_BASE:
            ir_id = TISCI_DEV_WKUP_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_WKUP_GPIO1;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721S2_DEV_WKUP_GPIO1 */
            break;
        case (uint32_t)CSL_GPIO0_BASE:
            ir_id = TISCI_DEV_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_GPIO0;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721S2_DEV_GPIO0 */
            break;
        case (uint32_t)CSL_GPIO2_BASE:
            ir_id = TISCI_DEV_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_GPIO2;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721S2_DEV_GPIO2 */
            break;
        case (uint32_t)CSL_GPIO4_BASE:
            ir_id = TISCI_DEV_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_GPIO4;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721S2_DEV_GPIO4 */
            break;
        case (uint32_t)CSL_GPIO6_BASE:
            ir_id = TISCI_DEV_GPIOMUX_INTRTR0;
            src_id = TISCI_DEV_GPIO6;
            src_index = (uint16_t)bankNum;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721S2_DEV_GPIO6 */
            break;
        default:
            break;
    }

    /* Get TISCI Destination Idx for the core */
    dst_id = GPIO_socGetCoreSciId();

    /* Get valid Interrupt Idx for the core by querying from BoardCfg */
    retVal = GPIO_socGetIrqRange(ir_id, dst_id, &irq_range_start, &irq_range_num);

    if(CSL_PASS == retVal) 
    {
        if(bankNum <= irq_range_num)
        {
            // dst_host_irq = irq_range_start + bankNum;
            dst_host_irq = 396;
        #if defined (BUILD_C7X)
            intCfg[pinNum].eventId  = dst_host_irq; /* CLEC i/p Event Idx - Use Range from BoardCfg */ 
            intCfg[pinNum].intNum  += bankNum;      /* CLEC o/p to C7x core  */
        #else
            intCfg[pinNum].intNum   = dst_host_irq; /* Core Interrupt Idx - Use Range from BoardCfg */ 
        #endif
        }
        else
        {
            retVal = CSL_EFAIL;
        }
    }

    appLogPrintf("[debug][%s:%d] portNum=%d, pinNum=%d\n", __func__, __LINE__, portNum, pinNum);

    appLogPrintf("[debug][%s:%d] src_id=%d, TISCI_DEV_GPIO2=%d, J721S2_DEV_GPIO2=%d\n", __func__, __LINE__, 
                                                src_id, TISCI_DEV_GPIO0, J721S2_DEV_GPIO0);

    appLogPrintf("[debug][%s:%d] src_index=%d\n", __func__, __LINE__, src_index);

    appLogPrintf("[debug][%s:%d] dst_id=%d, TISCI_DEV_R5FSS0_CORE0=%d, J721S2_DEV_R5FSS0_CORE0=%d\n", __func__, __LINE__, 
                                          dst_id, TISCI_DEV_R5FSS0_CORE0,J721S2_DEV_R5FSS0_CORE0);
    appLogPrintf("[debug][%s:%d] dst_host_irq=%d\n", __func__, __LINE__, dst_host_irq);

    if(CSL_PASS == retVal) 
    {
        /* Config event */
        if(setIntrPath) 
        {
            (void)memset (&rmIrqReq,0,sizeof(rmIrqReq));

            rmIrqReq.secondary_host   = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
            rmIrqReq.src_id           = src_id;
            rmIrqReq.src_index        = src_index;  /* This is the event coming out of the peripheral */

            /* Set the destination interrupt */
            rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
            rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

            rmIrqReq.dst_id       = dst_id;
            rmIrqReq.dst_host_irq = dst_host_irq;

            if(0U == GPIO_PinBankUsageCount[portNum][bankNum]) 
            {
                retVal = Sciclient_rmIrqSet(
                            (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                            &rmIrqResp,
                            SCICLIENT_SERVICE_WAIT_FOREVER);
                appLogPrintf("[debug][%s:%d] Sciclient_rmIrqSet retVal=%d\n", __func__, __LINE__, retVal);
                if(CSL_PASS == retVal) 
                {
                    /* Increase the bank usage count for this port */
                    GPIO_PinBankUsageCount[portNum][bankNum]++;
                }
            } 
            else 
            {
                /* The interrupt path is already allocated, no need to re-allocate it */
                retVal = CSL_PASS;
            }
        } 
        else 
        {
            (void)memset (&rmIrqRelease,0,sizeof(rmIrqRelease));

            rmIrqRelease.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
            rmIrqRelease.src_id         = src_id;
            rmIrqRelease.src_index      = src_index;  /* This is the event coming out of the peripheral */

            /* Set the destination interrupt */
            rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
            rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

            /* Set the destination based on the core */
            rmIrqRelease.dst_id       = dst_id;
            rmIrqRelease.dst_host_irq = dst_host_irq;

            retVal = Sciclient_rmIrqRelease(
                            (const struct tisci_msg_rm_irq_release_req *)&rmIrqRelease,
                            SCICLIENT_SERVICE_WAIT_FOREVER);

            if(CSL_PASS == retVal) 
            {
                /* Decrease the bank usage count for this port */
                GPIO_PinBankUsageCount[portNum][bankNum]--;
            }
        }

    #if defined (BUILD_C7X)
        int32_t               ret;
        CSL_ClecEventConfig   cfgClec;
        CSL_CLEC_EVTRegs     *clecBaseAddr = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;

        /* Configure CLEC for GPIO */
        cfgClec.secureClaimEnable = FALSE;
        cfgClec.evtSendEnable     = TRUE;
    #if defined(BUILD_C7X_1)
        cfgClec.rtMap             = CSL_CLEC_RTMAP_CPU_4;
    #elif defined(BUILD_C7X_2)
        cfgClec.rtMap             = CSL_CLEC_RTMAP_CPU_5;
    #endif
        cfgClec.extEvtNum         = 0;
        cfgClec.c7xEvtNum         = intCfg[pinNum].intNum;
        ret = CSL_clecConfigEvent(clecBaseAddr, intCfg[pinNum].eventId, &cfgClec);
        if (ret == CSL_EFAIL)
        {
            retVal = CSL_EFAIL;
        }
    #endif
    }

  return(retVal);
}

The results of the following four runs

[MCU2_0]     13.670338 s: [debug][GPIO_socConfigIntrPath:534] portNum=0, pinNum=59
[MCU2_0]     13.670455 s: [debug][GPIO_socConfigIntrPath:536] src_id=111, TISCI_DEV_GPIO2=111, J721S2_DEV_GPIO2=111
[MCU2_0]     13.670583 s: [debug][GPIO_socConfigIntrPath:539] src_index=3
[MCU2_0]     13.670677 s: [debug][GPIO_socConfigIntrPath:541] dst_id=279, TISCI_DEV_R5FSS0_CORE0=279, J721S2_DEV_R5FSS0_CORE0=279
[MCU2_0]     13.670811 s: [debug][GPIO_socConfigIntrPath:543] dst_host_irq=396
[MCU2_0]     13.671006 s: [debug][GPIO_socConfigIntrPath:569] Sciclient_rmIrqSet retVal=-1

We need the GPIO interrupt handler, now the bank interrupt does not work, can you tell me how to modify the code for the independent GPIO interrupt?

Hi Renf Shi,

can you please search TI e2e? I have supported many tickets where i had explained how we can get individual GPIO interrupt.

Even the faq at below link shows similar request. You would have remove UDMA specific portion from below faq and then you can get individual GPIO interrupt. Please note we require to use different SciClient API to configure GPIOMux router for getting individual GPIO interrupt. 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1061801/faq-tda4vm-gpio-dma-trigger-in-tda4-and-test-in-sdk7-1

Regards,

Brijesh

According to this link, I have the following questions:

1. What is the difference between Sciclient_rmIrqSetRaw and Sciclient_rmIrqSet,  and the parameters of Sciclient_rmIrqSetRaw  is src_id, src_index, dst_id, dst_host_irq, how should the parameters be defined?

2. How do I register an interrupted function Sciclient_rmIrqSetRaw?

Hi Renf Shi,

Renf Shi said:

1. What is the difference between Sciclient_rmIrqSetRaw and Sciclient_rmIrqSet,  and the parameters of Sciclient_rmIrqSetRaw  is src_id, src_index, dst_id, dst_host_irq, how should the parameters be defined?

Set API is supported to figure the entire path from source to destination and set it up. Whereas Raw API just configures individual interrupt router. So with raw API, src_id and dst_id are same ie id of the interrupt router. src index is the id of the GPIO, which is connected to the interrupt router and dst index is the output of the interrupt router. Please refer to below link for output id. Here column IR Output Index is what we need to provide as dest index and next three column provide information about where/how this output is connected to the destination. For example, output 19 is connected to all 4 main domain R5F on irq number 179.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/interrupt_cfg.html#gpiomux-intrtr0-interrupt-router-output-destinations

Renf Shi said:

2. How do I register an interrupted function Sciclient_rmIrqSetRaw?

This API just configures interrupt router and connects input GPIO interrupt to one of the output and then we can use corresponding irq number to register the interrupt. For example, for output 19, the irq number on R5F is 179.

Regards,

Brijesh

Below is the modified code, where these parameters are set based on your feedback, are they correct? But Sciclient_rmIrqSetRaw returns -1

static void App_pinmux(void)
{
    Uint32 regVal = 0U;
    /* Pinmux for  GPIO0_59 */
    regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
    HW_WR_REG32(BOARD_MAIN_PMUX_CTRL_ADDR + PIN_TIMER_IO1, regVal);
}

static void App_initGpio(uint32_t gpio_id)
{
    uint32_t chIdx, bitpos, bank_id;
    bitpos = gpio_id % 32;
    bank_id = gpio_id / 16;

    *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    *(volatile uint32_t *)0x00600054 = (1u << bitpos);

    *(volatile uint32_t *)0x0060005C = (1u << bitpos);

    *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x00600008 = (1u << bank_id);

    *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    *(volatile uint32_t *)0x00600054 = (1u << bitpos);
    
}

static void App_setupGpioMuxIr(void)
{
    int32_t                             status;
    // uint32_t                            chIdx = 22;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
    rmIrqReq.src_index      = 59;

    /* Set the destination based on the core */
    rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
    rmIrqReq.dst_host_irq   = 6;

    /* Set the destination interrupt */
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;


    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_index);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_host_irq);

    status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);
    issLogPrintf("[%s:%d] Sciclient_rmIrqSetRaw status=%d\n",__func__, __LINE__,status);
    if(status == CSL_PASS)
    {
        issLogPrintf ("Worked fine \n");
    }
    else
    {
        issLogPrintf ("Failed \n");
    }
}
void test_gpio_interrupt(void)
{
    Board_initCfg                       boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO | BOARD_INIT_UNLOCK_MMR |
        BOARD_INIT_PLL_MCU | BOARD_INIT_MODULE_CLOCK_MCU;
    Board_moduleClockEnable(TISCI_DEV_GPIO0);

    Board_init(boardCfg);
    App_pinmux();
    App_initGpio(GPIO_IMU_PIN_NUM);
    App_setupGpioMuxIr();

}

The result output of the run

[MCU2_0]     10.265171 s: [App_setupGpioMuxIr:348] src_id=148
[MCU2_0]     10.265289 s: [App_setupGpioMuxIr:349] src_id=59
[MCU2_0]     10.265375 s: [App_setupGpioMuxIr:350] src_id=148
[MCU2_0]     10.265457 s: [App_setupGpioMuxIr:351] src_id=6
[MCU2_0]     10.265649 s: [App_setupGpioMuxIr:357] Sciclient_rmIrqSetRaw status=-1
[MCU2_0]     10.265754 s: Failed

Hi Renf Shi,

The code looks correct, but we need to see the resources allocated on the core where you are running this code. It seems you are using mcu2_0 core. On this core, only 4 IRQs from GPIOMUX output are allocated in the RM. So instead of dst index as 6, can you try using index 24? 24 to 27 are allocated to mcu2_0.

Regards,

Brijesh

I did the dst index loop from 0-63, only 0 is successful, I use the interrupt number 396 by registering the interrupt callback function by Osal_RegisterInterrupt, Osal_RegisterInterrupt returns 0, but my callback function is still not called

Below is the modified code,

void gpio_callback_fuction(uintptr_t arg)
{
    issLogPrintf("imu interrupt...\n");
}


static void App_pinmux(void)
{
    Uint32 regVal = 0U;
    /* Pinmux for  GPIO0_59 */
    regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
    HW_WR_REG32(BOARD_MAIN_PMUX_CTRL_ADDR + PIN_TIMER_IO1, regVal);
}

static void App_initGpio(uint32_t gpio_id)
{
    uint32_t chIdx, bitpos, bank_id;
    bitpos = gpio_id % 32;
    bank_id = gpio_id / 16;

    *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    *(volatile uint32_t *)0x00600054 = (1u << bitpos);

    *(volatile uint32_t *)0x0060005C = (1u << bitpos);

    *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x00600008 = (1u << bank_id);

    *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    *(volatile uint32_t *)0x00600054 = (1u << bitpos);
    
}

static void App_setupGpioMuxIr(void)
{
    int32_t                             status;
    int32_t                             success = 0;
    // uint32_t                            chIdx = 22;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
   

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
    rmIrqReq.src_index      = 59;

    /* Set the destination based on the core */
    rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;

    rmIrqReq.dst_host_irq   = 0;

    /* Set the destination interrupt */
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
// try:

    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_index);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_host_irq);

    status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);
    issLogPrintf("[%s:%d] Sciclient_rmIrqSetRaw status=%d\n",__func__, __LINE__,status);
    if(status == CSL_PASS)
    {
        issLogPrintf ("Worked fine \n");
        success++;
    }
    else
    {
        issLogPrintf ("Failed \n");
        
    }
    // if(++rmIrqReq.dst_host_irq <= 63)
    // {
    //     TaskP_sleep(1000);
    //     goto try;
    // }
    issLogPrintf("[%s:%d] Sciclient_rmIrqSetRaw success=%d\n",__func__, __LINE__,success);
}

void reg_func(int intNum)
{
    OsalRegisterIntrParams_t    intrPrms;
    HwiP_Handle hwiHandle;
    OsalInterruptRetCode_e      osalRetVal;

    Osal_RegisterInterrupt_initParams(&intrPrms);
    intrPrms.corepacConfig.arg          = (uintptr_t)NULL;
    intrPrms.corepacConfig.isrRoutine   = &gpio_callback_fuction;
    intrPrms.corepacConfig.priority     = 1U;
    intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
    intrPrms.corepacConfig.intVecNum        = intNum;

    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    issLogPrintf("[%s:%d] Osal_RegisterInterrupt osalRetVal=%d\n",__func__, __LINE__,osalRetVal);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
         issLogPrintf ("Osal_RegisterInterrupt fail \n");
    }else{
         issLogPrintf ("Osal_RegisterInterrupt fine \n");
    }
}

void test_gpio_interrupt(void)
{
    Board_initCfg                       boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO | BOARD_INIT_UNLOCK_MMR |
        BOARD_INIT_PLL_MCU | BOARD_INIT_MODULE_CLOCK_MCU;
    Board_moduleClockEnable(TISCI_DEV_GPIO0);

    Board_init(boardCfg);
    App_pinmux();
    App_initGpio(GPIO_IMU_PIN_NUM);
    App_setupGpioMuxIr();
    reg_func(396);

}

The result output of the run

[MCU2_0]     10.201342 s: [App_setupGpioMuxIr:349] src_id=148
[MCU2_0]     10.201467 s: [App_setupGpioMuxIr:350] src_id=59
[MCU2_0]     10.201551 s: [App_setupGpioMuxIr:351] src_id=148
[MCU2_0]     10.201633 s: [App_setupGpioMuxIr:352] src_id=0
[MCU2_0]     10.201980 s: [App_setupGpioMuxIr:358] Sciclient_rmIrqSetRaw status=0
[MCU2_0]     10.202076 s: Worked fine 
[MCU2_0]     10.202124 s: [App_setupGpioMuxIr:374] Sciclient_rmIrqSetRaw success=1
[MCU2_0]     10.202238 s: [reg_func:391] Osal_RegisterInterrupt osalRetVal=0
[MCU2_0]     10.202336 s: Osal_RegisterInterrupt fine 

Hi,

Are you using default DM, which is released in SDK? Have you made any changes in the DM ie RM? Because i tried SDK8.6 yesterday for GPIO4_90 and i am able to receive interrupt on mcu2_0. So it does work fine in the SDK. Also is the 59 GPIO number for which you want to get the interrupt? 

I used below code for configuring GPIOMUX router.

static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0; //131
        rmIrqReq.src_index      = GPIO_START + chIdx; //90

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0; //131
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx; //24

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

        status = Sciclient_rmIrqSetRaw(
                   (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                    &rmIrqResp,
                    SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            App_print ("Worked fine \n");
        }
        else
        {
            App_print ("Failed \n");
        }
    }
}

Regards,

Brijesh

I don't have any changes to the configuration and code of DM or RM, I use the default, I need to use GPIO0_59 interrupt on the muc2_0, I looked at your configuration, why is the value of TISCI_DEV_GPIOMUX_INTRTR0 131 different from my 148, is the platform you tested TDA4VM? I am currently using TDA4AL

That's because i have tested this patch on TDA4VM, whereas you are using TDA4VL. 148 is correct value as per below link for GPIOmux.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/interrupt_cfg.html#gpiomux-intrtr0-interrupt-router-input-sources

ok, on TDA4VL, 4 outputs, starting from index 0, are allocated to mcu2_0. So dst_idx as 0 should pass in sciclient API. This is connected to interrupt number 396, so please this irq number. 

Can you please check if pinmux is setup correctly for this GPIO0_59? 

Regards,

Brijesh

I use the following code to configure pinmux, the read 0x4301C0EC value is 0x08214007, the lower 8 bits are 7, does it represent the GPIO function?

static void App_pinmux(void)
{
    Uint32 regVal = 0U;
    /* Pinmux for  GPIO0_59 */
    regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
    HW_WR_REG32(BOARD_MAIN_PMUX_CTRL_ADDR + PIN_TIMER_IO1, regVal);
}

Thank you very much for your help, the following last modified code can enter the break, thank you

void gpio_callback_fuction(uintptr_t arg)
{
    issLogPrintf("imu interrupt...\n");
}


static void App_pinmux(void)
{
    Uint32 regVal = 0U;
    /* Pinmux for  GPIO0_59 */
    // regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
    regVal = 0x50007;
    HW_WR_REG32(BOARD_MAIN_PMUX_CTRL_ADDR + PIN_TIMER_IO1, regVal);
}

static void App_initGpio(uint32_t gpio_id)
{
    uint32_t chIdx, bitpos, bank_id;
    bitpos = gpio_id % 32;
    bank_id = gpio_id / 16;

    // *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    // *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    // *(volatile uint32_t *)0x00600054 = (1u << bitpos);

    *(volatile uint32_t *)0x0060005C = (1u << bitpos);

    // *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    // *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

    *(volatile uint32_t *)0x00600008 = (1u << bank_id);

    // *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    // *(volatile uint32_t *)0x00600054 = (1u << bitpos);
    
}

static void App_setupGpioMuxIr(void)
{
    int32_t                             status;
    int32_t                             success = 0;
    // uint32_t                            chIdx = 22;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
   

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
    rmIrqReq.src_index      = 59;

    /* Set the destination based on the core */
    rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;

    rmIrqReq.dst_host_irq   = 0;

    /* Set the destination interrupt */
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
// try:

    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_index);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_id);
    issLogPrintf("[%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.dst_host_irq);

    status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);
    issLogPrintf("[%s:%d] Sciclient_rmIrqSetRaw status=%d\n",__func__, __LINE__,status);
    if(status == CSL_PASS)
    {
        issLogPrintf ("Worked fine \n");
        success++;
    }
    else
    {
        issLogPrintf ("Failed \n");
        
    }
    // if(++rmIrqReq.dst_host_irq <= 63)
    // {
    //     TaskP_sleep(1000);
    //     goto try;
    // }
    issLogPrintf("[%s:%d] Sciclient_rmIrqSetRaw success=%d\n",__func__, __LINE__,success);
}

void reg_func(int intNum)
{
    OsalRegisterIntrParams_t    intrPrms;
    HwiP_Handle hwiHandle;
    OsalInterruptRetCode_e      osalRetVal;

    Osal_RegisterInterrupt_initParams(&intrPrms);
    intrPrms.corepacConfig.arg          = (uintptr_t)NULL;
    intrPrms.corepacConfig.isrRoutine   = &gpio_callback_fuction;
    intrPrms.corepacConfig.priority     = 1U;
    intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
    intrPrms.corepacConfig.intVecNum        = intNum;

    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    issLogPrintf("[%s:%d] Osal_RegisterInterrupt osalRetVal=%d\n",__func__, __LINE__,osalRetVal);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
         issLogPrintf ("Osal_RegisterInterrupt fail \n");
    }else{
         issLogPrintf ("Osal_RegisterInterrupt fine \n");
    }
}

void test_gpio_interrupt(void)
{
    // Board_initCfg                       boardCfg;

    // boardCfg = BOARD_INIT_PINMUX_CONFIG |
    //     BOARD_INIT_MODULE_CLOCK |
    //     BOARD_INIT_UART_STDIO | BOARD_INIT_UNLOCK_MMR |
    //     BOARD_INIT_PLL_MCU | BOARD_INIT_MODULE_CLOCK_MCU;
    // Board_moduleClockEnable(TISCI_DEV_GPIO0);

    // Board_init(boardCfg);
    App_pinmux();
    App_initGpio(GPIO_IMU_PIN_NUM);
    App_setupGpioMuxIr();
    reg_func(396);

}