TDA2P-ACD: DSS video parallel output with resolution more than 1080p

Yumin Yin

Prodigy 40 points

Part Number: TDA2P-ACD

Dear TI colleague,

i have several questions regarding the Display subsystem (DSS) module.

1st question:

I only found DSS can support output up to 1080p @60fps via HDMI in datasheet.

My concern is if TDA2P-ACD can support the video output via parallel link with the following parameter:

Resolution&fps&Type: 2672*1936 @9fps YUV 422 (blanking about 20% additional)

Basically the pixel clock will be around 111MHz

btw. is there a specific limit scope on the DSS parallel output horizontal/vertical pixel like 1920x1080 60fps? or its just related to pixel clock.

2nd question:

I wanna ask if parallel video output can be switched directly from 1920*1080@60fps to 1200*800@30fps when device power supply is ON ?

or this kind of output switch need reinitialization of system?

Look forward to your reply

over 2 years ago

0 Brijesh Jadav over 2 years ago

TI__Guru**** 477985 points

Hi,

#1, No DSS does not support more than 2K (2047) resolution. Even if video port can support this resolution and fps, but video pipeline can support at max 2048 line width only..

#2, Switching from DSS perspective is simple. Turn off video port, reconfigure it for the new resolution and turn it on.

Regards,

Brijesh

0 Yumin Yin over 2 years ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

#1. If i understand correctly, the line width max. 2048 you mentioned means the horizontal/vertical resolution right ?

so that DSS can support max. 2048*2048 resolution ? what is the fps limit ?

Best regards

Yumin

+1 Brijesh Jadav over 2 years ago in reply to Yumin Yin

TI__Guru**** 477985 points

Hi Yuyin,

The fps depends on the pixel clock, If i remember, the max pixel clock supported is 190MHz.

Regards,

Brijesh

0 Yumin Yin over 2 years ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

after checking internally and considering the 190MHz max. PCLK of TDA2Pxx, the final proposed VOP as follows:

TDA2P-ACD video output via parallel link

Resolution & FPS &Type: 2047 * 1484 @15fps YUV422 (blanking +20% additional)

Pixel clock: 109MHz

Can TDA2P-ACD support such output ?

Best regards

Yumin

0 Brijesh Jadav over 2 years ago in reply to Yumin Yin

TI__Guru**** 477985 points

Hi Yumin,

Are you looking for 16bit output or 8bit output? Because for 8bit output, it would required 2x clock..

Regards,

Brijesh

0 Yumin Yin over 2 years ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

oh i forget to add this information in the description.

Its for 8bits output and the 109MHz already includes 2x clock

Yumin

0 Brijesh Jadav over 2 years ago in reply to Yumin Yin

TI__Guru**** 477985 points

Hi Yumin,

ok then, it seems it is possible. Please also note that HSW width is at max 256 clock cycles..

Regards,

Brijesh

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TDA2P-ACD: DSS video parallel output with resolution more than 1080p