AM625: Changing U-Boot console from UART0 to UART4

Katsuhiro Numata

Part Number: AM625

Hi,

Our custom board will use UART4 as a serial console.
Since the board is not yet complete, we are experimenting with AM62x-SK EVM.

We have modified the DTS of the U-Boot as follows:

diff --git a/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi b/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
index b57d9563d87..51397bfdfdd 100644
--- a/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
+++ b/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
@@ -68,11 +68,11 @@
 	u-boot,dm-spl;
 };
 
-&main_uart0 {
+&main_uart4 {
 	u-boot,dm-spl;
 };
 
-&main_uart0_pins_default {
+&main_uart4_pins_default {
 	u-boot,dm-spl;
 };
 
diff --git a/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common.dtsi b/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common.dtsi
index fd52bb2872e..a899b8394ea 100644
--- a/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/sdk/u-boot/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -14,7 +14,7 @@
 
 / {
 	aliases {
-		serial2 = &main_uart0;
+		serial2 = &main_uart4;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
 		mmc2 = &sdhci2;
@@ -141,10 +141,10 @@
 };
 
 &main_pmx0 {
-	main_uart0_pins_default: main-uart0-pins-default {
+	main_uart4_pins_default: main-uart4-pins-default {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
-			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+			AM62X_IOPAD(0x0124, PIN_INPUT, 3) /* (A23) MMC2_SDCD.UART4_RXD */
+			AM62X_IOPAD(0x0128, PIN_OUTPUT, 3) /* (B23) MMC2_SDWP.UART4_TXD */
 		>;
 	};
 
@@ -273,8 +273,7 @@
 };
 
 &main_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "disabled";
 };
 
 &main_uart1 {
@@ -291,7 +290,8 @@
 };
 
 &main_uart4 {
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart4_pins_default>;
 };
 
 &main_uart5 {

Then, a panic has occurred at serial_find_console_or_panic() in R5 SPL.
The cause seems to be that ti_clk_of_xlate() is returning an error.

In arch/arm/dts/k3-am65-main.dtsi, UART0 and UART4 are defined as follows:

main_uart0: serial@2800000 {
        compatible = "ti,am64-uart", "ti,am654-uart";
        reg = <0x00 0x02800000 0x00 0x100>;
        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 146 0>;
        clock-names = "fclk";
};

...

main_uart4: serial@2840000 {
        compatible = "ti,am64-uart", "ti,am654-uart";
        reg = <0x00 0x02840000 0x00 0x100>;
        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 155 0>;
        clock-names = "fclk";
};

We assume that the error is caused because the definition corresponding to clocks = <&k3_clks 155 0> does not exist in arch/arm/mach-k3/am62x/clk-data.c.

static const struct dev_clk soc_dev_clk_data[] = {
...
        DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
        DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
        DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
        DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
...
}

Could you please advise how to fix this problem?

over 1 year ago

0 Judith Mendez over 1 year ago

TI__Expert 8400 points

Hi,

I am looking into this issue, please allow some time for a response.

~ Judith

0 Judith Mendez over 1 year ago

TI__Expert 8400 points

Hi,

<&k3_clks 155 0> should be correct according to https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-uart4-device.

I am currently verifying this on my end. Question, how did you build u-boot and update the bootloaders?

Do you get any output on ttyUSB0?

~ Judith

0 Katsuhiro Numata over 1 year ago in reply to Judith Mendez

Prodigy 50 points

Hi,

Thank you for your reply.

I built u-boot and sysfw-image using a Makefile equivalent to the top level Makefile, then I stored tiboot3.bin on the SD card.

https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM62X/08_06_00_42/exports/docs/linux/Overview/Top_Level_Makefile.html

How can I get output on ttyUSB0?

By the way, our custom board will be modified to use UART0, so this question is no longer urgent. But I think someone else will face the same problem.

Best regards,

0 Judith Mendez over 1 year ago in reply to Katsuhiro Numata

TI__Expert 8400 points

Hi,

How can I get output on ttyUSB0?

Connect USB cable to UART port (J15) and Linux machine. Then open with minicom or picocom or alike to look at debug prints from U-boot and Linux kernel.

By the way, our custom board will be modified to use UART0, so this question is no longer urgent. But I think someone else will face the same problem.

-- Sure, some things to do:
1) Update u-boot environment
2) Update chosen node in u-boot device tree, stdout-path and bootargs
3) Update device tree for Linux kernel.

Please refer to the following threads for more info:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/944121/am4378-ttys6-9-stands-for-what
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/965944/j721exsomxevm-linux-kernel-hangs-at-starting-kernel

~ Judith

0 Katsuhiro Numata over 1 year ago in reply to Judith Mendez

Prodigy 50 points

Hi,

I understood that ttyUSB0 means serial console output of U-Boot and Linux.
There is no serial output (ttyUSB0) because the panic occurs when U-Boot initializes the serial console.

(1) Sorry, I haven't tried this, but I don't see any definition corresponding to <&k3_clks 155 0> even in the latest sources, so I assume the situation is the same. arch/arm/mach-k3/am62x/clk-data.c

DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 20, "clkout0_ctrl_out0"),

(2) Do I need to change something in stdout-path? I think bootargs is a Linux boot parameter and does not affect U-Boot. arch/arm/dts/k3-am62x-r5-sk-common.dtsi

chosen {
        stdout-path = "serial2:115200n8";
        tick-timer = &timer1;
};

(3) Since the panic occurs at the U-Boot stage, I believe the Linux kernel device tree is irrelevant.

I don't mind if this question is closed, but I don't think it has been resolved.

Best regards,

0 Judith Mendez over 1 year ago in reply to Katsuhiro Numata

TI__Expert 8400 points

Hi,

Will look at this and respond by tomorrow.

~ Judith

0 Judith Mendez over 1 year ago in reply to Judith Mendez

TI__Expert 8400 points

Hi Katsuhiro,

The engineer who works on clock tree for AM62x is out for holiday and will not be back. When they get back I will update why we do not have that clock in the auto-generated file for AM62x. Sorry for the delay.

~ Judith

0 Judith Mendez over 1 year ago in reply to Judith Mendez

TI__Expert 8400 points

Hi Katsuhiro

Could you try the following files and try again.

dev-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62X specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
	[4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]),
	[3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]),
	[4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
	[5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[10]),
	[6] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[7] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[8] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[9] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[10] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[11] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[12] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
	[13] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[12]),
	[14] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[12]),
	[15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[14]),
	[16] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[14]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(170, &soc_lpsc_list[1]),
	PSC_DEV(177, &soc_lpsc_list[2]),
	PSC_DEV(55, &soc_lpsc_list[3]),
	PSC_DEV(178, &soc_lpsc_list[4]),
	PSC_DEV(179, &soc_lpsc_list[5]),
	PSC_DEV(54, &soc_lpsc_list[6]),
	PSC_DEV(80, &soc_lpsc_list[6]),
	PSC_DEV(57, &soc_lpsc_list[7]),
	PSC_DEV(58, &soc_lpsc_list[8]),
	PSC_DEV(161, &soc_lpsc_list[9]),
	PSC_DEV(162, &soc_lpsc_list[10]),
	PSC_DEV(75, &soc_lpsc_list[11]),
	PSC_DEV(102, &soc_lpsc_list[12]),
	PSC_DEV(146, &soc_lpsc_list[12]),
	PSC_DEV(155, &soc_lpsc_list[12]),
	PSC_DEV(13, &soc_lpsc_list[13]),
	PSC_DEV(166, &soc_lpsc_list[14]),
	PSC_DEV(135, &soc_lpsc_list[15]),
	PSC_DEV(136, &soc_lpsc_list[16]),
};

const struct ti_k3_pd_platdata am62x_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = 2,
	.num_pd = 5,
	.num_lpsc = 17,
	.num_devs = 24,
};

clk-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62X specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
	"clk_32k_rc_sel_div_clkout",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gpmc_fclk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout3_clk",
	"postdiv4_16ff_main_2_hsdivout7_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv1_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const char * const main_usart4_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out4",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_gpmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("gpmc_main_0_po_gpmc_dev_clk", 0, 0),
	CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x68209c, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gpmc_fclk_sel_out0", main_gpmc_fclk_sel_out0_parents, 2, 0x108180, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out4", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108250, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_MUX("main_usart4_fclk_sel_out0", main_usart4_fclk_sel_out0_parents, 2, 0x108290, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
	DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
	DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
	DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
	DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
	DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(54, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(80, 0, "main_gpmc_fclk_sel_out0"),
	DEV_CLK(80, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(80, 2, "postdiv4_16ff_main_2_hsdivout7_clk"),
	DEV_CLK(80, 3, "board_0_gpmc0_clklb_out"),
	DEV_CLK(80, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(155, 0, "main_usart4_fclk_sel_out0"),
	DEV_CLK(155, 1, "usart_programmable_clock_divider_out4"),
	DEV_CLK(155, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(155, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 34, "gpmc_main_0_po_gpmc_dev_clk"),
	DEV_CLK(157, 36, "gpmc_main_0_po_gpmc_dev_clk"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
	DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
	DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
	DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
	DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
	DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
	DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
	DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
	DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 1, "board_0_tck_out"),
	DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62x_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = 96,
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = 149,
};

~ Judith

0 Katsuhiro Numata over 1 year ago in reply to Judith Mendez

Prodigy 50 points

Hi,

Thank you for providing the files.

After replacing arch/arm/mach-k3/mach-k3/am62x/clk-data.c and arch/arm/mach-k3/am62x/dev-data.c with the files you provided, the panic no longer occurs during serial console initialization.

However, another panic occurred in k3_sysfw_loader().

The same problem occurred with the U-Boot included in SDK 08.05.00.21, where I replaced only clk-data.c and dev-data.c. Here are the serial output and the screenshot of the debugger.

U-Boot SPL 2021.01-00001-g5b0d5e5347-dirty (Jul 07 2023 - 18:55:06 +0900)
alloc space exhausted
k3_system_controller sysctrler: k3_of_to_priv: Acquiring boot_notify channel failed. ret = -19
k3_system_controller sysctrler: k3_sysctrler_probe: Probe failed with error -19
rproc failed to be initialized (-19)

resetting ...

I also tried with SDK08.06.00.42, but the build failed with the following error.

~/ti-processor-sdk-linux-rt-am62xx-evm-08.06.00.42$ make u-boot

...

  COPY    spl/u-boot-spl.bin
/home/ijp/ti-processor-sdk-linux-rt-am62xx-evm-08.06.00.42/board-support/u-boot-2021.01+gitAUTOINC+2ee8efd654-g2ee8efd654/tools/k3_gen_x509_cert.sh -c 16 -b spl/u-boot-spl.bin \
                        -o tiboot3.bin -l 0x43c00000 -r 1 -k ""
 SWRV = 1
spl/u-boot-spl.bin exceeds file size limit:
  limit:  0x30220 bytes
  actual: 0x30558 bytes
  excess: 0x338 bytes
/home/ijp/ti-processor-sdk-linux-rt-am62xx-evm-08.06.00.42/board-support/u-boot-2021.01+gitAUTOINC+2ee8efd654-g2ee8efd654/Makefile:1929: recipe for target 'spl/u-boot-spl.bin' failed
make[2]: *** [spl/u-boot-spl.bin] Error 1
make[2]: *** Deleting file 'spl/u-boot-spl.bin'
make[2]: Leaving directory '/home/ijp/ti-processor-sdk-linux-rt-am62xx-evm-08.06.00.42/board-support/u-boot_build/r5'
Makefile:167: recipe for target 'sub-make' failed
make[1]: *** [sub-make] Error 2
make[1]: Leaving directory '/home/ijp/ti-processor-sdk-linux-rt-am62xx-evm-08.06.00.42/board-support/u-boot-2021.01+gitAUTOINC+2ee8efd654-g2ee8efd654'
Makefile:244: recipe for target 'u-boot-r5' failed
make: *** [u-boot-r5] Error 2

Unfortunately, it is difficult for me to investigate this issue further.

Best regards,

0 Judith Mendez over 1 year ago in reply to Katsuhiro Numata

TI__Expert 8400 points

Hi,

We run out of space in malloc. Will try to send another .c that is pruned.

~Judith

+1 Judith Mendez over 1 year ago in reply to Judith Mendez

TI__Expert 8400 points

Hello,

Try the following source files:

2350.clk-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62X specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
	"clk_32k_rc_sel_div_clkout",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv1_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart4_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out4",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out4", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108250, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart4_fclk_sel_out0", main_usart4_fclk_sel_out0_parents, 2, 0x108290, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
	DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
	DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
	DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
	DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
	DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(155, 0, "main_usart4_fclk_sel_out0"),
	DEV_CLK(155, 1, "usart_programmable_clock_divider_out4"),
	DEV_CLK(155, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(155, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
	DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
	DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
	DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
	DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
	DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
	DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
	DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
	DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 1, "board_0_tck_out"),
	DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62x_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = 90,
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = 137,
};

6518.dev-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62X specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
	[4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]),
	[3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]),
	[4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
	[6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
	[12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]),
	[13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]),
	[14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]),
	[15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(170, &soc_lpsc_list[1]),
	PSC_DEV(177, &soc_lpsc_list[2]),
	PSC_DEV(55, &soc_lpsc_list[3]),
	PSC_DEV(178, &soc_lpsc_list[4]),
	PSC_DEV(179, &soc_lpsc_list[5]),
	PSC_DEV(57, &soc_lpsc_list[6]),
	PSC_DEV(58, &soc_lpsc_list[7]),
	PSC_DEV(161, &soc_lpsc_list[8]),
	PSC_DEV(162, &soc_lpsc_list[9]),
	PSC_DEV(75, &soc_lpsc_list[10]),
	PSC_DEV(102, &soc_lpsc_list[11]),
	PSC_DEV(155, &soc_lpsc_list[11]),
	PSC_DEV(13, &soc_lpsc_list[12]),
	PSC_DEV(166, &soc_lpsc_list[13]),
	PSC_DEV(135, &soc_lpsc_list[14]),
	PSC_DEV(136, &soc_lpsc_list[15]),
};

const struct ti_k3_pd_platdata am62x_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = 2,
	.num_pd = 5,
	.num_lpsc = 16,
	.num_devs = 21,
};

~ Judith

0 Katsuhiro Numata over 1 year ago in reply to Judith Mendez

Prodigy 50 points

Hi,

Thank you for providing the files again.

I have tried them and the U-Boot SPL on the R5 core seemed to run to the end.

Since we are trying them on SK-EVM, I can't see the output of UART4, but they seem to work well.

Thank you for your assistance. I hope this thread will be helpful to someone else.

Best regards.

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Processors

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AM625: Changing U-Boot console from UART0 to UART4