The thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1088251/tda4vm-r5f-mpu-config is locked for some reason so I can't post my answer there. Here's the answer to the question:
What I do not understand is, that the memory read/write performance for "Non-Cacheable" Memory (TEX[2:0] = 001, C = 1, B = 1) and "Cacheable" Memory (TEX[2:0] = 101, C = 0, B = 1) is the same according to my tests. Also, it makes little sense, to declare a region "Non-Cacheable" but on the other hand, the description says "Outer and Inner write-back, write-allocate.", does it?
The difference between TEX[2]=1 and TEX[2]=0 is that the former allows you to set outer and inner policies separately while when TEX[2]=0, they are always the same. In both cases, when C=1, caching is enabled. Setting different policies is important when the backing memory is an intermediate cache (like L2 or L3 or even L1). However, if you don't care to set outer policy and inner policy separately, use the TEX[2]=0 encoding.
Thanks
Vai
