AM623: DP83825i PHY further schematic review request

Hello Josh Green,

Thank you for the query.

We do not support schematics review over E2E. Since this is specific to the Ethernet interface, we should be able to support.

The SoC IOs are not failsafe and so i would be interested in understanding the power supply source for the Ethernet supplies and the SoC IO supplies including the voltage level for VDDSHV2.

In case you have any constraint sharing the supply related schematics, do let me know for me to continue the review.

Regards,

Sreenivasa

Hi Sreenivasa,

I have included the power section along with the updated PHY section after Gokul's remarks. 

The plan is to run the PHY VDDIO at 3V3, using CLKOUT0 as a 50MHz source to the RMII bus and PHY (PHY in slave mode as per DP83825i reqs.)

One of the areas I would like to be double checked are the CLKOUT0 connections to the PHY and to the RMII REF CLK input. 

As the clock signal is split in a Y, I plan to make the branch of the split that is RMII REF_CLK (from R83 to U1.AD17) the same trace length as the other RMII signals plus the branch of the clock that runs to the PHY XI input (R80 to U4.13). I am ignoring the length of the tail of the Y split. 

Essentially I plan to delay the RMII REF_CLK signal with respect the the other RMII signals to mitigate the delay from the clock split and through the PHY.

PHY.pdf

SoM Power.pdf

 Hello Josh Green,

Thank you for the inputs.

Looks like the SoC and the PHY is powered by 3.3V supply.

The CLKOUT0 need to be buffered and the buffer needs to be placed at the center of the SoC and the PHY. The distance to the PHY and the SoC from the buffer output is expected to be similar to minimize effect of the clock timing on the interface.

Using two-output phase aligned buffer is highly recommended.

Refer  schematics checklist 

https://www.ti.com/lit/an/sprad21b/sprad21b.pdf

Section below 

7.3.1.4 Ethernet PHY (and MAC) Operation and MII Interface Clock

The EPHY reset may need an external pulldown to hold the PHY in reset until the SoC powers and configures the internal pulldown.

The PHY should be held in reset until the clock is configured and stable.

Regards,

Sreenivasa

Hi Sreenivasa,

Thank you for your comments and link to the schematic checklist. 

Regarding the clock buffer, would the LMK1C1102 be suitable?

I guess it's a case of costing up the crystal versus the clock buffer. It's a shame the CLKOUT0 pin cannot be used directly as that would be the most cost-effective solution.

Can the CLKOUT0 frequency be set to 25MHz when using RMII mode? In the TRM I can see registers for configuring the CLKOUT0 frequency for Ethernet Boot, but in parenthesis it says either RMII or RGMII mode.

AM62x TRM section: 5.6.7 Ethernet Boot Parameter Table

If the CLKOUT0 was 25MHz and we simply used this as a clock source to the PHY XI/OSCIN pin, I could set the PHY to be a controller and generate the 50MHz RMII refclk internally. If this is possible, would you still be recommending a clock buffer for CLKOUT0? The reason the PHY cannot be a controller now, is that the DP83825i must receive 25MHz on the OSCIN, not 50MHz for master mode.

Hello Josh Green,

Thank you for the note. 

Josh Green said:

I guess it's a case of costing up the crystal versus the clock buffer. It's a shame the CLKOUT0 pin cannot be used directly as that would be the most cost-effective solution.

Understand your concerns and good that the observations were made before board fab.

You should be able to use the PHY in master mode. I would suggest using the WKUP_CLKOUT0 that provides 25M output by default.

I would assume the data sheet recommendations have been considered while choosing the 25 M SoC clock.

In case of the Master configuration, try to place the PHY closer to the SoC.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for bringing the WKUP_CLKOUT0 to my attention. It looks like this is an internally buffered clock output and should provide me the signal needed to run the PHY directly and in master mode.

Configuring it this way should also simplify length matching and routing a little bit too.

The crystal we have chosen for the processor has the following specs: f=25MHz, CL=10pF, CShunt=5pFmax, Tol=+-10ppm, Stability=+-10ppm, Drive=100uW, ESR=30Rmax

Thanks for all your help :)