AM6412: The customized board boot failure and DDR0_RESET0_n signal has no action

Hi Daniel,

Thank you for the query. 

I have taken your inputs. Please allow some time to revert back.

Regards,

Tushar

Hi Daniel, 

Daniel Cheng1 said:

Is there a timing diagram for the sequence relationship between DDR0_RESET0_n and MCU_RESETSTATz, RESETSTATz, PORz_OUT signals?

On TI's EVM during start-up the DDR reset is expect to be low, when the SoC starts working and access the DDR it will make it high.

Daniel Cheng1 said:

But DDR0_RESET0_n signal is still low.

Do you have a suggested to debug?

I am routing your query to our hardware expert, and will get a response in one or two days.

Thanks & Regards,

Tushar

Hello Daniel, 

I need additional information on the custom board to verify the DDR interface and associated power supplies.

Please let me know if this is something you would be able to share.

Regards,

Sreenivasa

Hi Sreenivasa

Please let me know what information is needed

Thanks

Daniel

Hello Daniel, 

Thank you for the note.

I will need schematics in searchable PDF to be able to verify the DDR interface and associated circuit including power supply.

Regards,

Sreenivasa

Hi Sreenivasa

Could you give me the email, I will send the schematics in searchable PDF to you

Thanks

Daniel

Hello Daniel, 

Thank you.

Please share over private chat.

Regards,

Sreenivasa

Hi Sreenivasa

I have sent schematics and power sequence via private message.

Thanks for your help.

Daniel

Hello Daniel,

Thank you. 

I see one page for the AM6442 power supplies.

Did you share the DDR interface schematics?

Regards,

Sreenivasa

Hi Sreenivasa

TLE3-400-12_CPU_V090_20230509A.pdf is power supplies

am6412_FAE_20230307A_P05.pdf is DDR.

Thanks

Daniel

Hello Daniel,

Thank you for the note.

Can you please confirm if R391 and 392 are mounted.

Please DNI R391 as below and do a quick check.

Regards,

Sreenivasa

Hi Sreenivasa

update schematics over private chat.

R391 REMOVE
J15 connect to GND

But the issue is same

Thanks

Daniel

Hello Daniel,,

Thank you.

Do you see any activity on the reset during power-up.

I see another thread. Is this for the same board.

(+) AM6412: customer board can not boot - Processors forum - Processors - TI E2E support forums

Could you please help verify the source of the below supply.

VDDSHVy_1V8

J15 - please provide some inputs.

Regards,

Sreenivasa

Hi Sreenivasa

Do you see any activity on the reset during power-up

>>Did you mean PORz_OUT? Reset state? Or DDR_RESET_N?

>>Both PORz_OUT and RESETSTATz have risen, but DDR_RESET_N has not risen.

Could you please help verify the source of the supply VDDSHVy_1V8

>>PWR has been up, PMIC has also issued PWRGD, and all power rails have been confirmed.

J15 - please provide some inputs on the connector
>>Should the J15 of SR2.0 Silicon be powered by 1.8V or connected to GND? Or connected to which side?

Thanks

Daniel

Hello Daniel,,

Thank you.

Is this issue happening on a specific board or multiple boards. 

Although nor specific to this issue, here are some changes that could be tried.

C56 4.7uF/10V 0402 - we are recommending 3.3uF 

L17, L25 and L26 - Did you try shorting these ferrites 

Daniel Cheng1 said:

Should the J15 of SR2.0 Silicon be powered by 1.8V or connected to GND? Or connected to which side?

J15 is ADC0_REFP, 1.8 V

Regards,

Sreenivasa

Hi Sreenivasa

Errata means SR2.0 silicon: If VDDS_MMC0 and VDDA_ADC0 have different voltages, the ADC0_REFP (J15) voltage cannot be higher than VDDA_ADC0

Is it correct that VDDA_ADC0 is connected to ground and ADC0_REFP (J15) is connected to 1.8V?

PROC100A(002)_SCH J15 is also connected to the ground (the circuit in the figure below).

Thanks

Daniel

Hello Daniel,

Thank you for the additional query.

When partial schematics are provided we typically end up reviewing only the query customer asks.

For the ADC related

In case of the SK the ADC is not used 

ADC reference is as below 

The reference and the ADC VDDA are grounded

In case ADC is not used this is the recommended configuration.

Regards,

Sreenivasa