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DRA821U: Unhandled Exception in EL3

wang liu
Intellectual 261 points

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

hi 

    The current software and hardware environment is as follows:

sdk:8.04

ddr: 1333 mts

hardware: dra821

     During the power on/off test, the system encountered occasional EL3 errors,The approximate probability of occurrence is one in a thousand

There are several types of errors in printing.

==========================error 1 start =========================

NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
NOTICE: BL31: Built : 16:11:58, Sep 29 2022
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC:
I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Wed Sep 14 09:41:07 UTC 2022 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2021.01-g (Jul 06 2023 - 10:35:26 +0800)
Model: Texas Instruments K3 J7200 SoC
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
Trying to boot from MMC1
NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
NOTICE: BL31: Built : 16:11:58, Sep 29 2022
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC:
I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Wed Sep 14 09:41:07 UTC 2022 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot
Unhandled Exception in EL3.
x30 = 0x0000000070001a0c
x0 = 0x0000000070009000
x1 = 0x000000007000ebc0
x2 = 0x0000000000000100
x3 = 0x0000000000c50838
x4 = 0x0000000000000000
x5 = 0x0000000000000000
x6 = 0x0000000070010360
x7 = 0x0000000000000000
x8 = 0x000000009e8931d8
x9 = 0x0000000000000000
x10 = 0x0000000000000000
x11 = 0x0000000000000000
x12 = 0x0000000000000000
x13 = 0x0000000000000000
x14 = 0x0000000000000000
x15 = 0x0000000000000000
x16 = 0x0000000000000000
x17 = 0x0000000000000000
x18 = 0x0000000000000e38
x19 = 0x0000000000009ed0
x20 = 0x0000000070009ed0
x21 = 0x0000000000000000
x22 = 0x0000000000000000
x23 = 0x0000000000000000
x24 = 0x0000000000000000
x25 = 0x0000000080024250
x26 = 0x0000000000041044
x27 = 0x0000000080a22020
x28 = 0x0000000000000000
x29 = 0x000000007000b360
scr_el3 = 0x0000000000000e38
sctlr_el3 = 0x0000000030cd183f
cptr_el3 = 0x0000000000000000
tcr_el3 = 0x0000000080803520
daif = 0x00000000000003c0
mair_el3 = 0x00000000004404ff
spsr_el3 = 0x00000000800002cc
elr_el3 = 0x0000000070001a24
ttbr0_el3 = 0x0000000070011cc0
esr_el3 = 0x0000000096000006
far_el3 = 0x0000000000009ed0
spsr_el1 = 0x0000000000000000
elr_el1 = 0x0000000000000000
spsr_abt = 0x0000000000000000
spsr_und = 0x0000000000000000
spsr_irq = 0x0000000000000000
spsr_fiq = 0x0000000000000000
sctlr_el1 = 0x0000000000c8180d
actlr_el1 = 0x0000000000000000
cpacr_el1 = 0x0000000000000000
csselr_el1 = 0x0000000000000000
sp_el1 = 0x0000000000000000
esr_el1 = 0x0000000000000000
ttbr0_el1 = 0x0000000000000000
ttbr1_el1 = 0x0000000000000000
mair_el1 = 0x0000000000000000
amair_el1 = 0x0000000000000000
tcr_el1 = 0x0000000080803fa0
tpidr_el1 = 0x0000000000000000
tpidr_el0 = 0x0000000000000000
tpidrro_el0 = 0x0000000000000000
par_el1 = 0x0000000000000000
mpidr_el1 = 0x0000000080000000
afsr0_el1 = 0x0000000000000000
afsr1_el1 = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1 = 0x0000000000000000
cntp_ctl_el0 = 0x0000000000000000
cntp_cval_el0 = 0x0000000000000000
cntv_ctl_el0 = 0x0000000000000000
cntv_cval_el0 = 0x0000000000000000
cntkctl_el1 = 0x0000000000000000
sp_el0 = 0x000000007000b360
isr_el1 = 0x0000000000000000
dacr32_el2 = 0x0000000000000000
ifsr32_el2 = 0x0000000000000000
cpuectlr_el1 = 0x0000001b00000040
cpumerrsr_el1 = 0x0000000000000000
l2merrsr_el1 = 0x0000000000000000

==========================error 1 end=========================

==========================error 2 start=========================

NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
NOTICE: BL31: Built : 16:11:58, Sep 29 2022
Unhandled Exception in EL3.
x30 = 0x0000000070005e08
x0 = 0x0000000000000001
x1 = 0x000000007000a010
x2 = 0x000000007000a000
x3 = 0x0000000032801000
x4 = 0x0000000032401000
x5 = 0x0000000000000040
x6 = 0x00000000700119c8
x7 = 0x0000000000000000
x8 = 0x000000007001ffff
x9 = 0x0000000070011b98
x10 = 0x0000000032c80000
x11 = 0x0000000000000000
x12 = 0x0000000000809008
x13 = 0x000000000121302a
x14 = 0x0000000002102a20
x15 = 0x0000000080000200
x16 = 0x00000000500801c0
x17 = 0x0000000070000784
x18 = 0x0000000000000010
x19 = 0x000000007000922d
x20 = 0x000000007000b330
x21 = 0x0000000000000000
x22 = 0x0000000000000000
x23 = 0x0000000000000000
x24 = 0x0000000000005080
x25 = 0x0000000045000000
x26 = 0x0000000010200800
x27 = 0x0000000002212000
x28 = 0x0000000000800000
x29 = 0x000000007000b2c0
scr_el3 = 0x0000000000000238
sctlr_el3 = 0x0000000030cd183f
cptr_el3 = 0x0000000000000000
tcr_el3 = 0x0000000080803520
daif = 0x00000000000003c0
mair_el3 = 0x00000000004404ff
spsr_el3 = 0x00000000600002cc
elr_el3 = 0x0000000070002dd4
ttbr0_el3 = 0x0000000070011cc0
esr_el3 = 0x0000000096000006
far_el3 = 0x0000000032802000
spsr_el1 = 0x0000000000000010
elr_el1 = 0x0000000000022080
spsr_abt = 0x0000000000000010
spsr_und = 0x0000000000000010
spsr_irq = 0x0000000000000010
spsr_fiq = 0x0000000000000010
sctlr_el1 = 0x0000000000c50838
actlr_el1 = 0x0000000000000000
cpacr_el1 = 0x0000000000000000
csselr_el1 = 0x0000000000000000
sp_el1 = 0x0000000010828082
esr_el1 = 0x0000000000000000
ttbr0_el1 = 0x0000000000000000
ttbr1_el1 = 0x0000000000000000
mair_el1 = 0x44e048e000098aa4
amair_el1 = 0x0000000000000000
tcr_el1 = 0x0000000000000000
tpidr_el1 = 0x0000000000000000
tpidr_el0 = 0x0000000000000000
tpidrro_el0 = 0x0000000000000000
par_el1 = 0x0000000000000000
mpidr_el1 = 0x0000000080000000
afsr0_el1 = 0x0000000000000000
afsr1_el1 = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1 = 0x0000000000000000
cntp_ctl_el0 = 0x0000000000000000
cntp_cval_el0 = 0x0000000000000000
cntv_ctl_el0 = 0x0000000000000000
cntv_cval_el0 = 0x0000000000000000
cntkctl_el1 = 0x0000000000000000
sp_el0 = 0x000000007000b2c0
isr_el1 = 0x0000000000000000
dacr32_el2 = 0x0000000055555555
ifsr32_el2 = 0x0000000000000000
cpuectlr_el1 = 0x0000001b00000040
cpumerrsr_el1 = 0x0000000000000000
l2merrsr_el1 = 0x0000000000000000

==========================error 2 end=========================

==========================error 3 start=========================

NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
NOTICE: BL31: Built : 16:11:58, Sep 29 2022
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC:
I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Wed Sep 14 09:41:07 UTC 2022 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2021.01-g (Jun 21 2023 - 11:37:45 +0800)
Model: Texas Instruments K3 J7200 SoC
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
Trying to boot from MMC1
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] Linux version 5.10.120+ (oe-user@oe-host) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Wed Jun 21 11:37:45 CST 2023
[ 0.000000] Machine model: Texas Instruments K3 J7200 SoC
[ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
Unhandled Exception in EL3.
x30 = 0x0000000070001a7c
x0 = 0x0000000070009000
x1 = 0x000000007000ec40
x2 = 0x000000009e80fe5c
x3 = 0x0000008000000100
x4 = 0x0000000000000001
x5 = 0x0000000000000000
x6 = 0x00000000700105f0
x7 = 0x0000000000000000
x8 = 0x000000009e896278
x9 = 0x000000009e803000
x10 = 0x0000000000000000
x11 = 0x0000000000000000
x12 = 0x0000000000000000
x13 = 0x0000000000000000
x14 = 0x0000000000000000
x15 = 0x0000000000000000
x16 = 0x0000000000000000
x17 = 0x0000000000000000
x18 = 0x0000000000000e38
x19 = 0x0000000000009ed0
x20 = 0x0000000070009ed0
x21 = 0x0000000000000001
x22 = 0x0000000000000001
x23 = 0x0000000000000000
x24 = 0x000000009e80fe5c
x25 = 0x0000008000000100
x26 = 0x0000000000000001
x27 = 0x00000000700105f0
x28 = 0x00000000700105d0
x29 = 0x000000007000b9a0
scr_el3 = 0x0000000000000e38
sctlr_el3 = 0x0000000030cd183f
cptr_el3 = 0x0000000000000000
tcr_el3 = 0x0000000080803520
daif = 0x00000000000003c0
mair_el3 = 0x00000000004404ff
spsr_el3 = 0x00000000800002cc
elr_el3 = 0x0000000070001aa4
ttbr0_el3 = 0x0000000070011cc0
esr_el3 = 0x0000000096000006
far_el3 = 0x0000000000009ed0
spsr_el1 = 0x0000000000000000
elr_el1 = 0x0000000000000000
spsr_abt = 0x0000000000000000
spsr_und = 0x0000000000000000
spsr_irq = 0x0000000000000000
spsr_fiq = 0x0000000000000000
sctlr_el1 = 0x0000000000c8180d
actlr_el1 = 0x0000000000000000
cpacr_el1 = 0x0000000000000000
csselr_el1 = 0x0000000000000000
sp_el1 = 0x000000009e86b4a0
esr_el1 = 0x0000000000000000
ttbr0_el1 = 0x000000009e88b020
ttbr1_el1 = 0x0000000000000000
mair_el1 = 0x00000000ff00ff04
amair_el1 = 0x0000000000000000
tcr_el1 = 0x0000000080803fa0
tpidr_el1 = 0x0000000000000000
tpidr_el0 = 0x0000000000000000
tpidrro_el0 = 0x0000000000000000
par_el1 = 0x0000000000000000
mpidr_el1 = 0x0000000080000001
afsr0_el1 = 0x0000000000000000
afsr1_el1 = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1 = 0x000000009e803000
cntp_ctl_el0 = 0x0000000000000000
cntp_cval_el0 = 0x0000000000000000
cntv_ctl_el0 = 0x0000000000000000
cntv_cval_el0 = 0x0000000000000000
cntkctl_el1 = 0x0000000000000000
sp_el0 = 0x000000007000b9a0
isr_el1 = 0x0000000000000000
dacr32_el2 = 0x0000000000000000
ifsr32_el2 = 0x0000000000000000
cpuectlr_el1 = 0x0000001b00000040
cpumerrsr_el1 = 0x0000000000000000
l2merrsr_el1 = 0x0000000000000000
Unhandled Exception in EL3.
x30 = 0x0000000070001a7c
x0 = 0x0000000070009000
x1 = 0x000000007000ebc0
x2 = 0x00000000e7f811e3
x3 = 0x00000000af630002
x4 = 0x00000000a5d5c51b
x5 = 0x0000000000000000
x6 = 0x0000000070010360
x7 = 0x0000000000000000
x8 = 0x0000000000000000
x9 = 0x000000009e803000
x10 = 0x0000000000000000
x11 = 0x0000000000000000
x12 = 0x0000000000000000
x13 = 0x0000000000000000
x14 = 0x0000000000000000
x15 = 0x0000000000000000
x16 = 0x0000000000000000
x17 = 0x0000000000000000
x18 = 0x0000000000000e38
x19 = 0x0000000000009ed0
x20 = 0x0000000070009ed0
x21 = 0x0000000000000000
x22 = 0x0000000000000005
x23 = 0x00000000384fb3e0
x24 = 0x00000000e7f811e3
x25 = 0x00000000af630002
x26 = 0x00000000a5d5c51b
x27 = 0x0000000070010360
x28 = 0x0000000070010340
x29 = 0x000000007000b330
scr_el3 = 0x0000000000000e38
sctlr_el3 = 0x0000000030cd183f
cptr_el3 = 0x0000000000000000
tcr_el3 = 0x0000000080803520
daif = 0x00000000000003c0
mair_el3 = 0x00000000004404ff
spsr_el3 = 0x00000000800002cc
elr_el3 = 0x0000000070001aa4
ttbr0_el3 = 0x0000000070011cc0
esr_el3 = 0x0000000096000006
far_el3 = 0x0000000000009ed0
spsr_el1 = 0x0000000000000000
elr_el1 = 0x0000000000000000
spsr_abt = 0x0000000000000000
spsr_und = 0x0000000000000000
spsr_irq = 0x0000000000000000
spsr_fiq = 0x0000000000000000
sctlr_el1 = 0x0000000000c8180d
actlr_el1 = 0x0000000000000000
cpacr_el1 = 0x0000000000000000
csselr_el1 = 0x0000000000000000
sp_el1 = 0x000000009e86b450
esr_el1 = 0x0000000000000000
ttbr0_el1 = 0x000000009e88b000
ttbr1_el1 = 0x0000000000000000
mair_el1 = 0x00000000ff00ff04
amair_el1 = 0x0000000000000000
tcr_el1 = 0x0000000080803fa0
tpidr_el1 = 0x0000000000000000
tpidr_el0 = 0x0000000000000000
tpidrro_el0 = 0x0000000000000000
par_el1 = 0xff0000009fc00b80
mpidr_el1 = 0x0000000080000000
afsr0_el1 = 0x0000000000000000
afsr1_el1 = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1 = 0x000000009e803000
cntp_ctl_el0 = 0x0000000000000000
cntp_cval_el0 = 0x0000000000000000
cntv_ctl_el0 = 0x0000000000000000
cntv_cval_el0 = 0x0000000000000000
cntkctl_el1 = 0x0000000000000000
sp_el0 = 0x000000007000b330
isr_el1 = 0x0000000000000000
dacr32_el2 = 0x0000000000000000
ifsr32_el2 = 0x0000000000000000
cpuectlr_el1 = 0x0000001b00000040
cpumerrsr_el1 = 0x0000000000000000
l2merrsr_el1 = 0x0000000000000000

==========================error 3 end=========================

  • 0
    Intellectual 261 points

    Add the following information:

    We're trying  to increase  the voltage of the vdd_cpu by 40ms, increase  the voltage of the vdd_core iby 40ms, 

    No improvement in the problem.

  • +1 in reply to wang liu
    TI__Guru**** 170660 points
    wang liu said:

    We're trying  to increase  the voltage of the vdd_cpu by 40ms, increase  the voltage of the vdd_core iby 40ms, 

    All of them are happening around ATF. This is something not seen at our end. Have you measured the CPU/CORE voltages if yes what are the values?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 261 points
    Keerthy J said:

    We're trying  to increase  the voltage of the vdd_cpu by 40ms, increase  the voltage of the vdd_core iby 40ms, 

    All of them are happening around ATF. This is something not seen at our end. Have you measured the CPU/CORE voltages if yes what are the values?

      Both VDD_CPU and VDD_CORE voltages are 0.8v.

  • 0 in reply to wang liu
    TI__Guru**** 170660 points

    Wang,

    Thanks so did you check with .85V and see that it failed again?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 261 points

    The problem still exists with the 0.85V of vdd_core and vdd_cpu

  • 0 in reply to wang liu
    TI__Guru**** 170660 points

    Hi Wang,

    Is this a custom board or TI EVM? If custom board have you adapted the DDR changes for the custom board?
    Also are you using the pre-built ATF binary?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 261 points

    hi Keerthy

       This is our own board， the DDR changes for the own board  is Adapted,  the DDR changes is configure by SPRACU8B_Jacinto7_DDRSS_RegConfigTool(V0.10.0).

      Both the pre-built ATF binary and the ATF binary  compiled by yocto have all been tested.The problem still exists.

  • 0 in reply to wang liu
    Intellectual 261 points

       Add the following information:

       The attachment is the configuration table for ddr. Could you please help review it.

    SPRACU8B_Jacinto7_DDRSS_RegConfigTool.rar

  • 0 in reply to wang liu
    TI__Mastermind 44230 points

    Hi,

    Can you also please let us know what memory you are using?

    Is this a new board design, or existing one that was previously working?

    How many boards have been tested and show this issue?

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Intellectual 261 points

    hi Kevin

        1. The specific model of ddr is MT53E512M32D1ZW-046 AIT:B     

        2. The ddr model mentioned above has been used on the tda4 platform and has been mass-produced, making it the first time it has been used on the dra821 platform.

        3. Currently, two boards have been tested with a random probability of approximately one in ten thousand.

  • 0 in reply to wang liu
    TI__Expert 4245 points

    According to this ticket, this may still related to DDR corruption you can try to make the DBI as enabled within the DDR configure tool and have a test. 

    in meanwhile, i'm adding other TI experts onto this thread to follow up with other suggestions and moving forward. 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1045593/unhandled-exception-in-el3 

  • 0 in reply to Xu(SH) Liu
    TI__Mastermind 26185 points

    You should ensure that the all critical setup timings (like in L2CTLR_EL1) are matching what the current ATF source documents (3 cycle latency setting is critical).  A periodic failure like being reported are known if the setup timings and A72 errata work arounds are not in place!!  You need to dump more of the internal SPR registers and ensure it matches what is coded here: 

               https://github.com/ARM-software/arm-trusted-firmware/blame/master/plat/ti/k3/common/k3_helpers.S

    The ESR_EL3 0000000096000006 means, a data abort on read, the FAR says its to 09ED0.  This appears in X19, without more flow information its hard to guess what the bad access to that address happened.  Non-handled timing setup or some code race bug are possible reasons.

    Regards,
    Richard W.
  • 0 in reply to Xu(SH) Liu
    Intellectual 261 points

    Hi Liu

        The problem still exists when make the DBI as enabled within the DDR configure tool.

  • 0 in reply to wang liu
    TI__Expert 4245 points

    please upload you "k3_helpers.S" from kernel source for Richard to review. 

    Also, please upload the using ddr_config.h header file in uboot for Kevin to review. 

    thanks 

  • 0 in reply to Xu(SH) Liu
    Intellectual 261 points

        The k3_helpers.S is as follows:

    k3_helpers.S

        the ddr_config.h file cannot be found in the u-boot project.

  • 0 in reply to wang liu
    TI__Expert 4245 points

    Change below settings from 3 cycles to 4 cycles "CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES ", rebuild the ATF firmware and replace/upgrade to your filesystem and have a try to reproduce your previous problem. 

    a72:
    mrs x0, CORTEX_A72_L2CTLR_EL1
    orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)

    And the ddr configure file generated by excel tool is "./arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi" for DRA821, please make sure your DBI configure makes different before and after enable it through this generated header file, and upload the one your using now. 

  • 0 in reply to Xu(SH) Liu
    TI__Mastermind 26185 points

    #1 You should add the missing errata settings into your build permanently:

    /* Enable L2 ECC and parity with inline data */
    orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
    orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
    msr CORTEX_A72_L2CTLR_EL1, x0

    mrs x0, CORTEX_A72_L2ACTLR_EL1
    /* Enable L2 UniqueClean evictions with data */
    orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
    msr CORTEX_A72_L2ACTLR_EL1, x0

    #2 Carry out the experiment as Xu has directed above to see if there is a behavior change then share the results.

  • 0 in reply to Xu(SH) Liu
    Intellectual 261 points

        Configuring DDR is done in the SBL component.By confirming the following registers, Dbi has been enabled.

    DDRSS_PHY_102 [8] = 1
    DDRSS_PHY_358 [8] = 1
    DDRSS_PHY_614 [8] = 1
    DDRSS_PHY_870 [8] = 1

        Regarding the update of file k3_helpers.S, I will verify and update the latest progress.

  • 0 in reply to Richard Woodruff
    Intellectual 261 points

        Regarding the two modifications mentioned, the currently patch modified is as follows. Please help review it.

    atf_patch.zip

       

        After updating the patch above, the problem still exists.

    There are several types of errors in printing.

    ==========================error 1 end=========================

    [Fri Aug 04 08:10:01.581 2023] NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
    [Fri Aug 04 08:10:01.581 2023] NOTICE: BL31: Built : 11:03:05, Aug 3 2023
    [Fri Aug 04 08:10:01.587 2023] ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
    [Fri Aug 04 08:10:01.612 2023] I/TC:
    [Fri Aug 04 08:10:01.612 2023] I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Thu Jun 29 06:58:02 UTC 2023 aarch64
    [Fri Aug 04 08:10:01.633 2023] I/TC: WARNING: This OP-TEE configuration might be insecure!
    [Fri Aug 04 08:10:01.633 2023] I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
    [Fri Aug 04 08:10:01.641 2023] I/TC: Primary CPU initializing
    [Fri Aug 04 08:10:01.649 2023] I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
    [Fri Aug 04 08:10:01.652 2023] I/TC: HUK Initialized
    [Fri Aug 04 08:10:01.652 2023] I/TC: Activated SA2UL device
    [Fri Aug 04 08:10:01.659 2023] I/TC: Enabled firewalls for SA2UL TRNG device
    [Fri Aug 04 08:10:01.659 2023] I/TC: SA2UL TRNG initialized
    [Fri Aug 04 08:10:01.665 2023] I/TC: SA2UL Drivers initialized
    [Fri Aug 04 08:10:01.665 2023] I/TC: Primary CPU switching to normal world boot
    [Fri Aug 04 08:10:01.670 2023] Unhandled Exception in EL3.
    [Fri Aug 04 08:10:01.676 2023] x30 = 0x0000000070003a50
    [Fri Aug 04 08:10:01.676 2023] x0 = 0x000000000000a198
    [Fri Aug 04 08:10:01.681 2023] x1 = 0x0000000070011000
    [Fri Aug 04 08:10:01.681 2023] x2 = 0x0000000000000002
    [Fri Aug 04 08:10:01.686 2023] x3 = 0x0000000000000700
    [Fri Aug 04 08:10:01.686 2023] x4 = 0x0000000000000290
    [Fri Aug 04 08:10:01.692 2023] x5 = 0x0000000000000000
    [Fri Aug 04 08:10:01.697 2023] x6 = 0x0000000070010360
    [Fri Aug 04 08:10:01.697 2023] x7 = 0x0000000000000000
    [Fri Aug 04 08:10:01.703 2023] x8 = 0x000000009e8931d8
    [Fri Aug 04 08:10:01.703 2023] x9 = 0x0000000041023060
    [Fri Aug 04 08:10:01.710 2023] x10 = 0x0000000000000040
    [Fri Aug 04 08:10:01.715 2023] x11 = 0x0000000070009cb0
    [Fri Aug 04 08:10:01.715 2023] x12 = 0x000000007000b320
    [Fri Aug 04 08:10:01.721 2023] x13 = 0x000000000000000a
    [Fri Aug 04 08:10:01.721 2023] x14 = 0x0000000070011bfc
    [Fri Aug 04 08:10:01.726 2023] x15 = 0x0000000070003908
    [Fri Aug 04 08:10:01.726 2023] x16 = 0x000000000000007e
    [Fri Aug 04 08:10:01.731 2023] x17 = 0x000000009e800194
    [Fri Aug 04 08:10:01.738 2023] x18 = 0x0000000000000e38
    [Fri Aug 04 08:10:01.738 2023] x19 = 0x0000000070010340
    [Fri Aug 04 08:10:01.743 2023] x20 = 0x0000000000000000
    [Fri Aug 04 08:10:01.743 2023] x21 = 0x0000000000000000
    [Fri Aug 04 08:10:01.750 2023] x22 = 0x0000000000000000
    [Fri Aug 04 08:10:01.750 2023] x23 = 0x000000009e8018e4
    [Fri Aug 04 08:10:01.755 2023] x24 = 0x0000000000000002
    [Fri Aug 04 08:10:01.765 2023] x25 = 0x0000000000000700
    [Fri Aug 04 08:10:01.765 2023] x26 = 0x0000000000000001
    [Fri Aug 04 08:10:01.767 2023] x27 = 0x0000000070010360
    [Fri Aug 04 08:10:01.767 2023] x28 = 0x0000000070010340
    [Fri Aug 04 08:10:01.772 2023] x29 = 0x000000007000b2b0
    [Fri Aug 04 08:10:01.780 2023] scr_el3 = 0x0000000000000e38
    [Fri Aug 04 08:10:01.780 2023] sctlr_el3 = 0x0000000030cd183f
    [Fri Aug 04 08:10:01.783 2023] cptr_el3 = 0x0000000000000000
    [Fri Aug 04 08:10:01.783 2023] tcr_el3 = 0x0000000080803520
    [Fri Aug 04 08:10:01.789 2023] daif = 0x00000000000003c0
    [Fri Aug 04 08:10:01.789 2023] mair_el3 = 0x00000000004404ff
    [Fri Aug 04 08:10:01.794 2023] spsr_el3 = 0x00000000800002cc
    [Fri Aug 04 08:10:01.800 2023] elr_el3 = 0x0000000070004c2c
    [Fri Aug 04 08:10:01.800 2023] ttbr0_el3 = 0x0000000070011cc0
    [Fri Aug 04 08:10:01.806 2023] esr_el3 = 0x0000000096000006
    [Fri Aug 04 08:10:01.806 2023] far_el3 = 0x000000000000a1c0
    [Fri Aug 04 08:10:01.811 2023] spsr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.811 2023] elr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.817 2023] spsr_abt = 0x0000000000000000
    [Fri Aug 04 08:10:01.823 2023] spsr_und = 0x0000000000000000
    [Fri Aug 04 08:10:01.823 2023] spsr_irq = 0x0000000000000000
    [Fri Aug 04 08:10:01.829 2023] spsr_fiq = 0x0000000000000000
    [Fri Aug 04 08:10:01.829 2023] sctlr_el1 = 0x0000000000c8180d
    [Fri Aug 04 08:10:01.834 2023] actlr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.840 2023] cpacr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.840 2023] csselr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.846 2023] sp_el1 = 0x000000009e86b450
    [Fri Aug 04 08:10:01.846 2023] esr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.852 2023] ttbr0_el1 = 0x000000009e88b000
    [Fri Aug 04 08:10:01.852 2023] ttbr1_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.857 2023] mair_el1 = 0x00000000ff00ff04
    [Fri Aug 04 08:10:01.863 2023] amair_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.863 2023] tcr_el1 = 0x0000000080803fa0
    [Fri Aug 04 08:10:01.869 2023] tpidr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.869 2023] tpidr_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.874 2023] tpidrro_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.874 2023] par_el1 = 0xff0000009fc00b80
    [Fri Aug 04 08:10:01.880 2023] mpidr_el1 = 0x0000000080000000
    [Fri Aug 04 08:10:01.885 2023] afsr0_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.885 2023] afsr1_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.891 2023] contextidr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.891 2023] vbar_el1 = 0x000000009e803000
    [Fri Aug 04 08:10:01.897 2023] cntp_ctl_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.897 2023] cntp_cval_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.903 2023] cntv_ctl_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.908 2023] cntv_cval_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.908 2023] cntkctl_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.914 2023] sp_el0 = 0x000000007000b2b0
    [Fri Aug 04 08:10:01.914 2023] isr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.920 2023] dacr32_el2 = 0x0000000000000000
    [Fri Aug 04 08:10:01.925 2023] ifsr32_el2 = 0x0000000000000000
    [Fri Aug 04 08:10:01.925 2023] cpuectlr_el1 = 0x0000001b00000040
    [Fri Aug 04 08:10:01.931 2023] cpumerrsr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.931 2023] l2merrsr_el1 = 0x0000000000000000

    ==========================error 1 end=========================

    ==========================error 2 end=========================

    [Fri Aug 04 08:10:01.581 2023] NOTICE: BL31: v2.6(release):v2.7-rc0-dirty
    [Fri Aug 04 08:10:01.581 2023] NOTICE: BL31: Built : 11:03:05, Aug 3 2023
    [Fri Aug 04 08:10:01.587 2023] ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
    [Fri Aug 04 08:10:01.612 2023] I/TC:
    [Fri Aug 04 08:10:01.612 2023] I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Thu Jun 29 06:58:02 UTC 2023 aarch64
    [Fri Aug 04 08:10:01.633 2023] I/TC: WARNING: This OP-TEE configuration might be insecure!
    [Fri Aug 04 08:10:01.633 2023] I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
    [Fri Aug 04 08:10:01.641 2023] I/TC: Primary CPU initializing
    [Fri Aug 04 08:10:01.649 2023] I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
    [Fri Aug 04 08:10:01.652 2023] I/TC: HUK Initialized
    [Fri Aug 04 08:10:01.652 2023] I/TC: Activated SA2UL device
    [Fri Aug 04 08:10:01.659 2023] I/TC: Enabled firewalls for SA2UL TRNG device
    [Fri Aug 04 08:10:01.659 2023] I/TC: SA2UL TRNG initialized
    [Fri Aug 04 08:10:01.665 2023] I/TC: SA2UL Drivers initialized
    [Fri Aug 04 08:10:01.665 2023] I/TC: Primary CPU switching to normal world boot
    [Fri Aug 04 08:10:01.670 2023] Unhandled Exception in EL3.
    [Fri Aug 04 08:10:01.676 2023] x30 = 0x0000000070003a50
    [Fri Aug 04 08:10:01.676 2023] x0 = 0x000000000000a198
    [Fri Aug 04 08:10:01.681 2023] x1 = 0x0000000070011000
    [Fri Aug 04 08:10:01.681 2023] x2 = 0x0000000000000002
    [Fri Aug 04 08:10:01.686 2023] x3 = 0x0000000000000700
    [Fri Aug 04 08:10:01.686 2023] x4 = 0x0000000000000290
    [Fri Aug 04 08:10:01.692 2023] x5 = 0x0000000000000000
    [Fri Aug 04 08:10:01.697 2023] x6 = 0x0000000070010360
    [Fri Aug 04 08:10:01.697 2023] x7 = 0x0000000000000000
    [Fri Aug 04 08:10:01.703 2023] x8 = 0x000000009e8931d8
    [Fri Aug 04 08:10:01.703 2023] x9 = 0x0000000041023060
    [Fri Aug 04 08:10:01.710 2023] x10 = 0x0000000000000040
    [Fri Aug 04 08:10:01.715 2023] x11 = 0x0000000070009cb0
    [Fri Aug 04 08:10:01.715 2023] x12 = 0x000000007000b320
    [Fri Aug 04 08:10:01.721 2023] x13 = 0x000000000000000a
    [Fri Aug 04 08:10:01.721 2023] x14 = 0x0000000070011bfc
    [Fri Aug 04 08:10:01.726 2023] x15 = 0x0000000070003908
    [Fri Aug 04 08:10:01.726 2023] x16 = 0x000000000000007e
    [Fri Aug 04 08:10:01.731 2023] x17 = 0x000000009e800194
    [Fri Aug 04 08:10:01.738 2023] x18 = 0x0000000000000e38
    [Fri Aug 04 08:10:01.738 2023] x19 = 0x0000000070010340
    [Fri Aug 04 08:10:01.743 2023] x20 = 0x0000000000000000
    [Fri Aug 04 08:10:01.743 2023] x21 = 0x0000000000000000
    [Fri Aug 04 08:10:01.750 2023] x22 = 0x0000000000000000
    [Fri Aug 04 08:10:01.750 2023] x23 = 0x000000009e8018e4
    [Fri Aug 04 08:10:01.755 2023] x24 = 0x0000000000000002
    [Fri Aug 04 08:10:01.765 2023] x25 = 0x0000000000000700
    [Fri Aug 04 08:10:01.765 2023] x26 = 0x0000000000000001
    [Fri Aug 04 08:10:01.767 2023] x27 = 0x0000000070010360
    [Fri Aug 04 08:10:01.767 2023] x28 = 0x0000000070010340
    [Fri Aug 04 08:10:01.772 2023] x29 = 0x000000007000b2b0
    [Fri Aug 04 08:10:01.780 2023] scr_el3 = 0x0000000000000e38
    [Fri Aug 04 08:10:01.780 2023] sctlr_el3 = 0x0000000030cd183f
    [Fri Aug 04 08:10:01.783 2023] cptr_el3 = 0x0000000000000000
    [Fri Aug 04 08:10:01.783 2023] tcr_el3 = 0x0000000080803520
    [Fri Aug 04 08:10:01.789 2023] daif = 0x00000000000003c0
    [Fri Aug 04 08:10:01.789 2023] mair_el3 = 0x00000000004404ff
    [Fri Aug 04 08:10:01.794 2023] spsr_el3 = 0x00000000800002cc
    [Fri Aug 04 08:10:01.800 2023] elr_el3 = 0x0000000070004c2c
    [Fri Aug 04 08:10:01.800 2023] ttbr0_el3 = 0x0000000070011cc0
    [Fri Aug 04 08:10:01.806 2023] esr_el3 = 0x0000000096000006
    [Fri Aug 04 08:10:01.806 2023] far_el3 = 0x000000000000a1c0
    [Fri Aug 04 08:10:01.811 2023] spsr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.811 2023] elr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.817 2023] spsr_abt = 0x0000000000000000
    [Fri Aug 04 08:10:01.823 2023] spsr_und = 0x0000000000000000
    [Fri Aug 04 08:10:01.823 2023] spsr_irq = 0x0000000000000000
    [Fri Aug 04 08:10:01.829 2023] spsr_fiq = 0x0000000000000000
    [Fri Aug 04 08:10:01.829 2023] sctlr_el1 = 0x0000000000c8180d
    [Fri Aug 04 08:10:01.834 2023] actlr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.840 2023] cpacr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.840 2023] csselr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.846 2023] sp_el1 = 0x000000009e86b450
    [Fri Aug 04 08:10:01.846 2023] esr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.852 2023] ttbr0_el1 = 0x000000009e88b000
    [Fri Aug 04 08:10:01.852 2023] ttbr1_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.857 2023] mair_el1 = 0x00000000ff00ff04
    [Fri Aug 04 08:10:01.863 2023] amair_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.863 2023] tcr_el1 = 0x0000000080803fa0
    [Fri Aug 04 08:10:01.869 2023] tpidr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.869 2023] tpidr_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.874 2023] tpidrro_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.874 2023] par_el1 = 0xff0000009fc00b80
    [Fri Aug 04 08:10:01.880 2023] mpidr_el1 = 0x0000000080000000
    [Fri Aug 04 08:10:01.885 2023] afsr0_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.885 2023] afsr1_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.891 2023] contextidr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.891 2023] vbar_el1 = 0x000000009e803000
    [Fri Aug 04 08:10:01.897 2023] cntp_ctl_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.897 2023] cntp_cval_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.903 2023] cntv_ctl_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.908 2023] cntv_cval_el0 = 0x0000000000000000
    [Fri Aug 04 08:10:01.908 2023] cntkctl_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.914 2023] sp_el0 = 0x000000007000b2b0
    [Fri Aug 04 08:10:01.914 2023] isr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.920 2023] dacr32_el2 = 0x0000000000000000
    [Fri Aug 04 08:10:01.925 2023] ifsr32_el2 = 0x0000000000000000
    [Fri Aug 04 08:10:01.925 2023] cpuectlr_el1 = 0x0000001b00000040
    [Fri Aug 04 08:10:01.931 2023] cpumerrsr_el1 = 0x0000000000000000
    [Fri Aug 04 08:10:01.931 2023] l2merrsr_el1 = 0x0000000000000000

    ==========================error 2 end=========================

  • 0 in reply to wang liu
    TI__Expert 4245 points

    Richard, this may need your advice and support to proceed. thanks. 

  • 0 in reply to Xu(SH) Liu
    TI__Mastermind 26185 points

    Hello,

    The patch looks OK on quick inspection.

    The read abort address seems pretty consistent.  The elr_el3 value changes in dumps, but perhaps that is due to code size changes during experiments.  What does the map file show is exists at 0x0000000070004c2c? Inspection of the instructions around the abort may give a clue about what is going on.  Perhaps some uninitialized value randomly comes up in a way which causes an abort when code accesses the uninitialized structure.

    Regards,
    Richard W.
  • 0 in reply to Richard Woodruff
    Intellectual 261 points

    Hello，

        The problem has been resolved by applying the patch modifications below.

    cab8ef7.diff.zip

         Regarding the modification of patch, there are the following issues that need to be confirmed. In the native boot. c code, there is an action to clear cache, which will occur during SD card startup. However, during SPI flash startup, there is no such action. What are the considerations?

  • +1 in reply to wang liu
    TI__Mastermind 26185 points

    Hello,

    Good finding to resolve the issue.

    If the R5's cache is enabled via MPU regions for 0x70000000 then a clean indeed is required to ensure dirty data has been pushed out of the R5 dcache and into the shared MSMC.  The R5 core does not participate in snooping (like the A72 and C7x do) so a flush to MSMC is needed to ensure other entities see consistent data for any shared locations.  An A72 doesn't need to do anything special to share data with msmc-direct-attached cluster cores or to the R5, but the R5 needs to explicitly invalidate or flush shared msmc ranges it needs to share with other cores as its cache is not hooked to msmc-snoop tracking.

    Its unclear to me if other examples make this area as non-cached (so no need to share) or if they flush.  If they are marked as cached then flushing is needed to ensure properly operation.  Failure to do that would require good luck in that data motion would cause a displacement based eviction.

    Regards,
    Richard W.