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AM625: UDMA(BCDMA) setting procedure for memory transfer from peripheral devices.

T.M.
Prodigy 80 points
Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG,

Hi experts,

<Question>
What is the correct procedure for setting up UDMA (BCDMA) for transferring memory from a peripheral?

I followed the procedure below to initialize, and an error occurred in step (3).

(1) Enable PSIL of peripheral CSI_RX_IF(SHIM)
(2) Open the UDMA channel (Udma_chOpen)
　・Channel type is UDMA_CH_TYPE_RX.
　・Set CSL_PSILCFG_DMSS_CSI_PSILS_THREAD_OFFSET (0x4700) for channel parameter [peerChNum]. 
(3) Configure UDMA rx channel (Udma_chConfigRx)
　・Initialize parameters using UdmaChRxPrms_init

Error: NAK response from SYSFW in RX flow control configuration, error occurred Sciclient_rmUdmapFlowCfg (udma_flow.c line:391).

The initialization code for UDMA is as follows.

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void ConfigUdma0(void)
{
int32_t retVal = UDMA_SOK;
uint32_t chType;
Udma_ChHandle chHandle;
Udma_ChPrms chPrms;
Udma_ChRxPrms rxPrms;
Udma_DrvHandle drvHandle = &gUdmaDrvObj[CONFIG_UDMA0];
chHandle = &gConfigUdma0ChObj;
/* Init channel parameters */
chType = UDMA_CH_TYPE_RX; //PSIL-RX channel type
UdmaChPrms_init(&chPrms, chType);
chPrms.peerChNum = CSL_PSILCFG_DMSS_CSI_PSILS_THREAD_OFFSET;
chPrms.fqRingPrms.ringMem = gConfigUdma0BlkCopyCh0RingMem;
chPrms.fqRingPrms.ringMemSize = UDMA_CONFIG_UDMA0_CH_0_RING_MEM_SIZE;
chPrms.fqRingPrms.elemCnt = UDMA_CONFIG_UDMA0_PSIL_CHRING_ELEM_CNT;
/* Open channel for block copy */
retVal = Udma_chOpen(drvHandle, chHandle, chType, &chPrms); //OK(retVal == 0)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

The Trace log for SYSFW looks like this.

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Configuring trace data version to: 0x03007
0x00421110: BasePort: TISCI_MSG_RECEIVED(TISCI Message interrupt handled): Queue ID: 2 Message ID: 1110
0x00820024: BasePort: TISCI_MSG_SENDER_HOST_ID(Message from secure host received): Queue ID: 2 Host ID: 36
0x4F8A00FF: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group given in RM boardcfg message: 0x00FF
0x4F8B0001: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group of configured resource: 0x0001
0x4F80001A: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device ID being validated: 26
0x4100001A: Resource Management: RING_CONFIGURE(Configure NavSS ring): RA device ID: 26
0x4F8A00FF: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group given in RM boardcfg message: 0x00FF
0x4F8B0001: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group of configured resource: 0x0001
0x4F80001A: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device ID being validated: 26
0x4100001A: Resource Management: RING_CONFIGURE(Configure NavSS ring): RA device ID: 26
0x41070000: Resource Management: RING_CONFIGURE(Configure NavSS ring): upper 16-bits of valid_params: 0x0000
0x410800BF: Resource Management: RING_CONFIGURE(Configure NavSS ring): lower 16-bits of valid_params: 0x00BF
0x4F8A00FF: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group given in RM boardcfg message: 0x00FF
0x4F8B0001: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group of configured resource: 0x0001
0x4F80001A: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device ID being validated: 26
0x4100001A: Resource Management: RING_CONFIGURE(Configure NavSS ring): RA device ID: 26
0x00421280: BasePort: TISCI_MSG_RECEIVED(TISCI Message interrupt handled): Queue ID: 2 Message ID: 1280
0x00820024: BasePort: TISCI_MSG_SENDER_HOST_ID(Message from secure host received): Queue ID: 2 Host ID: 36
0x4F8A00FF: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group given in RM boardcfg message: 0x00FF
0x4F8B0001: Resource Management: DEVGRP_VALIDATE(Validating device group of resource): Device group of configured resource: 0x0001
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

<Supplementary note>
・The environment is using mcu_plus_sdk_am62x_09_00_00_19.
・SDK：Code Composer Studio Version: 12.4.0.00007
・sysconfig 1.16.2
・SYSFW Trace is enabled.
・Goal: UDMA configuration for CSI_RX_IF peripheral in bare-metal environment.

  • 0
    TI__Mastermind 39131 points

    Hello T.M,

    I have looked at your code and understand that you are trying to configure CSI UDMA on R5F.

    You have configured chPrms. peerChNum = CSL_PSILCFG_DMSS_CSI_PSILS_THREAD_OFFSET seems to be wrong. Typically, these channel macros should be available under the UDMA_soc.h file, but they were not there, which means the UDMA channel allocation provision is not given for CSI periperhal on the R5F core.

    I am thinking that CSI streaming applications should be done on A53 cores rather than R5F cores. May I know why you are trying to implement on R5F cores instead of A53 cores?

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Prodigy 80 points

    Hi S.Anil,

    We will explain why we are trying to implement CSI on the R5F core.

    Since our products require high control response and computing performance, it is necessary to execute bare-metal control on the R5F core and arithmetic operations on the A53 core.
    Since the A53 core is dedicated to arithmetic operations, we plan to assign interface control, including MIPI CSI, to the R5F core.

    Q1. Regarding the fact that UDMA channel assignment provisions are not provided for CSI peripherals on the R5F core, does this mean that disabling controls are in place to their use on the SYSFW?
    From a hardware point of view, data flow should be completed only by CSI and UDMA, so isn't it possible to configure UDMA on any CPU?

    Q2. It seems that it is possible to change resources, etc. by loading Board Configuration against SYSFW, so is it possible to implement UDMA channel allocation on the R5F core using this function?

  • +1 in reply to T.M.
    TI__Guru* 82565 points

    Hello T.M

    Thank you for taking the time to explain your usage scenario. Unfortunately for AM625 family , we do not enable and support controlling complex peripherals like CSI and DSS from R5. The core is dedicated for SYSFW and while we have opened it up a bit more for some simple MCU+ SDK features like serial ports and GPIO , along with automotive usecases where it is used to run MCALs, there is no plan to support DMAs and CSI with this R5. This was not the envisioned used on system architecture and therefore there is no planned software support around this. 

    Regards

    Mukul