Part Number: TDA4VH-Q1
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about Nikhil Dasan reply:
the mcu2_1 complete mpu configuration:
/*
* Copyright (c) Texas Instruments Incorporated 2020
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*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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*/
#include <stdlib.h>
#include <stdint.h>
#include <ti/csl/arch/r5/csl_arm_r5.h>
#include <ti/csl/arch/r5/csl_arm_r5_mpu.h>
#include <ti/csl/arch/r5/interrupt.h>
#include <ti/csl/arch/r5/csl_cache.h>
#include <app_mem_map.h>
/*
* This structure specifies the entries for mpu configuration to override the
* default MPU configuration which is part of the CSL init.
*/
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
__attribute__ ((section(".mpu_cfg")));
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
{
{
/* Region 0 configuration: complete 32 bit address space = 4Gbits */
.regionId = 0U,
.enable = 1U,
.baseAddr = 0x0U,
.size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = 0U,
.memAttr = 0U,
},
{
/* Region 1 configuration: ATCM memory */
.regionId = 1U,
.enable = 1U,
.baseAddr = 0x0U,
.size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 2 configuration: make ATCM as cacheable */
.regionId = 2U,
.enable = 1U,
.baseAddr = 0x41000000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 3 configuration: make BTCM as cacheable */
.regionId = 3U,
.enable = 1U,
.baseAddr = 0x41010000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 4 configuration: MCU OCSRAM as cacheable */
.regionId = 4U,
.enable = 1U,
.baseAddr = 0x41C00000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 5 configuration: make all MSMC as cacheable */
.regionId = 5U,
.enable = 1U,
.baseAddr = 0x70000000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 6 configuration: 2 GB DDR RAM */
.regionId = 6U,
.enable = 1U,
.baseAddr = 0x80000000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)TRUE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
.memAttr = 0U,
},
{
/* Region 7 configuration: Ring buffer */
.regionId = 7U,
.enable = 1U,
.baseAddr = IPC_VRING_MEM_ADDR,
.size = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = 0U,
},
{
/* Region 8 configuration: Remaining noncache memory
* This needs to be aligned, so starting it at
* 0xB0000000 */
.regionId = 8U,
.enable = 1U,
.baseAddr = 0xB0000000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = 0U,
},
{
/* Region 10 configuration: MCU2-1 IPC */
.regionId = 9U,
.enable = 1U,
.baseAddr = DDR_MCU2_1_IPC_ADDR,
.size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = 0U,
},
{
/* Region 10 configuration: FREETECH_SHARED_MEM_ADDR */
.regionId = 10U,
.enable = 1U,
.baseAddr = FREETECH_SHARED_MEM_ADDR,
.size = CSL_ARM_R5_MPU_REGION_SIZE_32MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 0U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = 0U,
},
};
i have confirmed that there are no other regions below my newly added mpu configuration
