This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi TI experts,
As per https://www.ti.com/lit/an/spracx6/spracx6.pdf, Is it possible to set DDR firewalls to protect 0x5000 0000 to 0x57FF FFFF of FSS region and A72 does not have any permissions on these memory and how to?
Thanks
Hi henry wu,
For which core do you want to provide access to this section and for which core do you want to deny access?
Regards,
Brijesh
Hi Brijesh
MCU1_0 can access this section and A72 core can't access this section
BR
Hi henry wu,
I think code in the file packages\ti\boot\sbl\soc\k3\sbl_sci_client.c disables the firewall for the FSS0 region. Can you refer to above FAQ/AppNote and update this code to allow only mcu1_0 (and DMA) access to this region?
Regards,
Brijesh
Hi Brijesh,
I'm confused, Do you mean the firewall of FSS0 region(x5000 0000 to 0x57FF FFFF ) in 'packages/ti/boot/sbl/soc/k3/sbl_sci_client.c'
already enabled(MCU1_0 can access and A72 can't)?
If not. May you provide the detailed code changes? I can't find the patch in spracx6.pdf, just some code snippset.
Thanks
Hi henry wu,
The code here actually disables the firewall, so it needs to be changed and should be enabled allowing access to this region only to mcu1_0 and DMA.
Regards,
Brijesh
Hi Brijesh,
Thanks for your clarification.
Could you provide the reference code?
Thanks