Other Parts Discussed in Thread: DRA821
Hi TI
This thread is an extension of our guide on adjusting SDIO Drive Strength.
Can you please provide a guidance for EMI/EMC Test?
I understand that the customer is conducting EMI/EMC tests,
The SDIO port is reporting noise over the threshold and they need to improve it.
In addition to adjusting SDIO Strength, I would like to know if there are other methods such as PCB Debugging.
The customer replied that they were unable to see any effect from tuning the SDIO Strength.
I would like to introduce an EMI/EMC countermeasure guide for DRA821.
It would be great to have an EMI/EMC Noise Reduction guide like the following link.
I need a guide not only for power design, but also for high-speed interface peripherals such as SDIO/PCIe.
They are in a situation where they need to make PCB modifications to reinforce the circuit.
https://www.ti.com/lit/ml/slyp757/slyp757.pdf?ts=1691298964698
In the figure below, the problem is that the noise has been detected above the level marked in red.
Thanks.
Regards,
Jack