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AM68A: AM68A with DS90UB953

Martin Geike
Prodigy 60 points

Part Number: AM68A
Other Parts Discussed in Thread: CDCE6214, DS90UB953-Q1

I’ve got a question to AM68A in conjunction with a DS90UB953.

We have a display with a DS90UB914A deserializer. Both datasheets mentioned that they are compatible with each other. We require DVP mode in DS90UB953.

My Question is: How do we synchronize the clock between CSI from AM68A and DS90UB953? In SNLA270A (Backwards capability Modes) at page 6, note 2 it is mentioned that the input clock in DVP mode shall be synchronized with CSI clock. Since the processor does not have an input pin for synchronization we have a problem. We could not use the “same” clock frequency in AM68A CSI and external oscillator cause they are not synchronized.

One approach is the usage of a e.g CDCE6214 and route the CSI clock from processor over this IC to the DS90UB953 serializer and derive a synchronized input clock.

Or does this paragraph “only” mean, the input clock at serializer side  and the PCLK at deserializer side are the same frequency and "unrelated" to CSI clock.  (Functional block diagram, 7.2 in 953 Datasheet).

Have we misunderstood this paragraph or is there a much smarter solution?

  • 0
    TI__Guru**** 503225 points

    hi Martin,

    I am bit confused. display with ub953 -> ub914 SERDES and then synchronization with CSI of AM68A? and then you want to route the CSI clock from processor over this IC to the DS90UB953 serializer? I didnot get it. Why do want to route CSI input clock to ub953?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 60 points

    Hi Brijesh,

    as mentioned in document "DS90UB953-Q1 Backwards Compatibility Modes for
    Operation With Parallel Output Deserializers" (SNLA270A), at page 6, is written in the note :"CSI-2 input data provided to the DS90UB953-Q1 must be synchronized to the Input frequency applied to CLKIN when using DVP external clock mode. ..."

    We definitly require DVP mode to get the 953 working with the 914A. The AM68A do not provide a synchronized clock, which we can use as CLKIN. Therefore we thought, we have to generate a synchronized (CSI-CLK <-> CKLIN) clock.

    I don't get your question: The MIPI CSI Clock from AM68A is required for DS90UB953. My question is about the seperate CLKIN-Pin of the 953, which is mandatory in external DVP mode.

    Or does this paragraph in SNLA270A mean, the CLKIN frequency is the "same" as PCLK at deserializer side?

    Many thanks in advance!

    Best regards

    Martin

  • 0 in reply to Martin Geike
    TI__Guru**** 503225 points

    Hi Martin,

    This requires hep from ub953. I will reassign this ticket to our ub953 team, they will be able to help here. 

    Regards,

    Brijesh

  • 0 in reply to Martin Geike
    TI__Mastermind 27915 points

    Hello Martin, 

    The DS90UB953 requires a clock source in DVP mode. In your setup, is the CSI input coming from the AM68A? In camera applications, this synchronization typically refers to the camera and the serializer using the same input clock signal. 

    In table 15 of the SNLA270A document previously referred to, the relationship between the external clock in signal and CSI-2 clock rates are listed. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 60 points

    Hello Zoe,

    thanks for your reply!

    Yes, we will use the CSI from AM68A as input to DS90UB953. As indicated in table 15, the CLKIN and CSI clock have a constant ratio (depending on lanes, throughput, ...), but they are not synchronised with each other?

    So we calculate the required throughput on deserializer side, determine the RCLK and then the CLKIN (e.g. x1.5 in RAW12 HF mode)?

    Best regards,

    Martin

  • +1 in reply to Martin Geike
    TI__Mastermind 27915 points

    Hi Martin,

    Thank you for the clarification. The external CLKIN and CSI clock are synchronized with each other. For DVP mode, the 953 input clock will need to be synchronized with the CSI-2 data as mentioned. Since there is no ability to synchronize the two signals using the processor, I recommend using the CSI-2 clock and a clock generator to divide down the clock frequency. The output PCLK will then be generated in respect to the CLKIN and CSI-2 clocks used. Please let me know if you have any additional questions or concerns on this topic. 

    Best,

    Zoe