The L2 memory configuration for the C6678 device is as follows: • Total memory size is 4096KB • Each core contains 512KB of memory • Local starting address for each core is 0080 0000h L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses. For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000, for C66x CorePac Core 1 this is equivalent to 0x11800000, and for C66x CorePac Core 2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.
Can EDMA3 read memory data at address 0x00800000?
The result of my experiment is that EDMA3 can read the memory data of the global address 0x10800000, but it fails when reading the local address 0x00800000.
The experimental code is as follows：
#define L2_1_FirstAddr (char *)0x10800000
#define L2_1_EndAddr (char *)0x1080ffff
#define L2_2_FirstAddr (char *)0x10810000
#define L2_2_EndAddr (char *)0x1081ffff
#define MSMC_1_FirstAddr (char *)0x0c100000
#define MSMC_1_EndAddr (char *)0x0c10ffff
#define MSMC_2_FirstAddr (char *)0x0c110000
#define MSMC_2_EndAddr (char *)0x0c11ffff
#define DDR_1_FirstAddr (char *)0x80000000
#define DDR_1_EndAddr (char *)0x8000ffff
#define DDR_2_FirstAddr (char *)0x80100000
#define DDR_2_EndAddr (char *)0x8010ffff
DMA_ParaConfig( 0, 0 ,0x80000000 ,0Xffff, 0X1, 0x10800000 ,0XFFFFFFFF);
// DMA0 component 2 channels
DMA_Start( 0 , 0);
// DMA0 component 2 channels
// Return the DMA transfer status, 1 means the data transfer is over, 0 means it is not over.
while (!DMA_TransState( 0 , 0));
Can EDMA3 read memory data at address 0x00800000?
Regards，
Gary
